106results about How to "Shorten wire length" patented technology

The invention provides a three-dimensional memory and a manufacturing method of the three-dimensional memory. The three-dimensional memory comprises a core storage circuit and a peripheral circuit. Atleast one storage string is formed in the core storage circuit. The three-dimensional memory also comprises a substrate, wherein the peripheral circuit is formed on the substrate; a common source electrode line layer which is formed on the peripheral circuit and electrically connected with the peripheral circuit; and a doped semiconductor material layer which is formed on the common source electrode line layer, wherein the core storage region is arranged on the semiconductor material layer.

A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on routing grids lined in a Y direction which is a direction vertical to a power-supply wiring of the cell used in automatic placement & routing and has a shape extended in an X direction which is a direction in parallel with the power-supply wiring, more specifically such a shape that, for example, a longer-side dimension of the terminal is equal to ''a routing grid interval in the X direction+a wiring width. According to the constitution, a cell area is reduced, which advantageously leads to the reduction of a chip area.

This invention relates to one chip imbed module structure ,which comprises dielectric layer, at least one layer of semiconductor chip and at least one circuit structure, wherein, the structure is connected to semiconductor slice through several conductive structures; backward module structure is imbedded into electron device through dielectric layer circuit structure and electron devices. The invention chip module structure applies each electron device process to make the circuit structure connected to electron device through each conductor.

The invention provides a display panel and a display device to reduce the step width of the display panel. The display panel comprises a display area, a non-display area which comprises an integratedcircuit binding area and a fan-out area, signal lines which comprise first and second signal lines in the display area, and fan-out traces which comprise a first fan-out trace and a second fan-out trace. The first fan-out trace and the second fan-out trace are both located in the fan-out area. The first fan-out trace is electrically connected with the first signal line. The second fan-out trace iselectrically connected with the second signal line. The first fan-out trace is electrically connected with a first terminal of an integrated circuit binding area through a first side. The second fan-out trace is electrically connected with a second terminal of the integrated circuit binding area through a second side. The first side and the second side are two different sides in the integrated circuit binding area.

Provided is a method for manufacturing a printed-circuit board, which can form bumps at substantially identical heights on connection pads having different opening diameters of a solder resist. Diametrically-small bumps (78S), which are made high of solder balls (77) mounted in diametrically-small openings (71S) of a solder resist layer (70), are flattened to have the same height as that of the solder bumps (78P) of diametrically-large openings (71P). The solder bumps (78S) of the diametrically small openings (71S) and the solder bumps (78P) of the diametrically large openings (71P) are identical in the solder quantity. No connection occurs at the solder bumps (78S) of the diametrically small openings (71S) so that the connection reliability between an IC chip (90) and a multilayer printed-circuit board (10) can be retained.

The invention discloses a planar array microwave antenna for a dual-beam traffic information detection radar; the antenna is formed by connecting one group of 20 serial planar antenna units with another group of 20 serial planar antenna units in parallel, and a central side-feed form is used for feeding to an antenna array; the planar array microwave antenna for dual-beam traffic information detection radar has the advantages that a pair of antennas can produce two beam main lobes between which an included angle, namely the included angle between the beam main lobes of the dual-beam antenna is formed, and the included angle completely meets the demands of the dual-beam traffic information detection radar; the central side-feed form is more favorable for the integration of a radar transmitting-receiving assembly and the antenna; and furthermore, the wiring length of the radar transmitting-receiving assembly can be shortened to reduce the microwave radiation loss and reduce the radar cross section area.

The embodiment of the present invention provides an optical device which relates to the optical communication field, and can satisfy the impedance matching requirement of the high frequency signal transmission. The optical device comprises a first substrate, a second substrate and a transfer plate, a first conductive access is arranged on the upper surface of the first substrate, a second conductive access is arranged on the lower surface of the first substrate, and a third conductive access is arranged on the upper surface of the second substrate. A microstrip line structure is arranged on the transfer plate and comprises a transfer line arranged on the upper surface of the transfer plate, and the upper surface of the second substrate is opposite to the lower surface of the first substrate, wherein the second conductive access is attached to the third conductive access, and the transfer plate is arranged above the upper surface of the second substrate and is located in the third conductive access. One end of the transfer line is electrically connected with the first conductive access by threading, and the other end is connected with an internal element in the optical device by threading. The embodiment of the present is used for the optical device manufacture.

The invention discloses a low-cost traffic information detecting radar device. A microwave signal source generates a millimeter wave by adopting a dielectric oscillator; a receiving and transmitting assembly is used for receiving and transmitting a signal by a planar array antenna; a frequency mixer is used for outputting and transmitting an intermediate frequency signal to an intermediate frequency signal processing unit for processing; the processed intermediate frequency signal is transmitted to a digital signal processing unit; the digital signal processing unit is connected with a man-machine interface unit; and after the intermediate frequency signal containing traffic information is processed by the digital signal processing unit, the man-machine interface unit outputs the traffic information. The invention has the advantage of judging the existence of vehicles by utilizing speed information, thereby greatly reducing the cost.

The invention relates to a method for optimizing FPGA chip layout based on an area clock. The method comprises following steps: initializing a netlist; instantiating area clock buffers (rbufs) and registers (regs); determining the connection relationships between the rbufs and the regs; packaging one rbuf and multiple regs driven by the rbuf into a macrocell according to the connection relationships; carrying out global layout based on the macrocells; determining the layout area of each macrocell; carrying out partial layout in the layout area; and determining the layout location of each reg in each macrocell. According to the method provided by the invention, the physical locations of the registers driven by the same area clock can be arranged in a relatively small area; the FPGA layout is optimized; the wiring length of the follow-up clock line is reduced; the wiring performance is improved; and the power consumption of the FPGA chips is reduced.

The invention is to implement large capacity of a power conversion device without increasing size of the device. The provided power conversion device comprises: a first conductor electrode with a plate-shaped part and a vertical part, the plate-shaped part is connected with anode terminal or cathode terminal of a capacitor and roughly parallel mounted with planes setting each terminal so as to cover the capacitor group, the vertical part is connected with direct current side of the first power conversion circuit and vertical to the planes; and a second conductor electrode with a similar plate-shaped part, a part which is connected with vertical part of the first conductor electrode and vertical to the planes and a part which is connected with direct current side of the second power conversion circuit and vertical to the planes. Thus, degree of non-homogeneous of current running through each capacitor may be alleviated such that large capacity may be implemented without increasing size of the power conversion device.

The invention discloses a helical packaging structure of a light-emitting semiconductor chip and a light-emitting semiconductor light source device thereof. The helical packaging structure mainly comprises a cylindrical body, two conductive electrodes and a plurality of light-emitting semiconductor chips, wherein the cylindrical body and the two conductive electrodes are fixedly and integrally installed; the side wall of the cylindrical body is also provided with two helical insulation bars which are encircled on the side wall of the cylindrical body in parallel and divide the side wall of the cylindrical body into two relatively independent helical packaging surfaces, i.e. an anode packaging surface and a cathode packaging surface, wherein the anode packaging surface is electrically conducted with one conductive electrode, and the cathode packaging surface is electrically conducted with the other conductive electrode; and the light-emitting semiconductor chips are adhered to the anode packaging surface and the cathode packaging surface in an encircling manner and electrically connected to the two conductive electrodes in the manner of series connection and/or parallel connection. In the invention, more light-emitting semiconductor chips can not only be adhered to a smaller size, but also more uniform light-emitting arcs of 360 DEG can be obtained.

The invention relates to the field of wiring devices, in particular to a hidden wiring groove. The technical scheme mainly includes that the wiring groove comprises a grooved tube, a cabinet body of amachined cabinet comprises the grooved tube, the grooved tube comprises a first portion, a second portion and a third portion which are sequentially connected, the first portion is parallel to the third portion, the second portion is perpendicular to the first portion and the third portion, and a plurality of wiring holes are formed in the grooved tube. The hidden wiring groove has the advantagesthat a rectangular tube of the machined cabinet body serves as the wiring groove, the wiring groove is simple, compact and reasonable in structure, and cost is saved.

Disclosed are a synchronous motor having reduced torque pulsation while having a high torque and a system for driving a synchronous motor. Specifically disclosed is a synchronous motor which comprises a rotor (2) and a stator(3), and U-phase windings (91; 91a, 91b, and the like), V-phase windings (92; 92ab and the like), and W-phase windings (93; 93ac and the like) are wound around stator yoke portions each located between two adjacent stator teeth (7; 7a, 7ab, and the like). Each of the windings is wound in predetermined turns and in a predetermined direction such that timing differences between the timings at which a magnetic field generated at each of the stator teeth is maximized and those at which portions (10, 11, 11, and the like) between magnetic poles pass the stator teeth while the rotor (2) rotates, the timing differences being caused by a difference between the interval between the magnetic poles and that between the stator teeth, are compensated.

The invention provides a gas detection alarm device which comprises acquisition devices. The acquisition devices are arranged in an underground environment and are used for acquiring various environmental parameters in real time, and output ends of the acquisition devices are connected with input ends of a microprocessor by wires; output ends of the microprocessor are respectively connected with an alarm device and a power switch used for controlling underground power supply circuits; a relay router is interactively connected with the microprocessor, and underground information is wirelessly transmitted to an upper computer of a ground monitoring center by the relay router. The gas detection alarm device has the advantages that serious accidents of gas combustion and explosion can be fundamentally greatly reduced owing to the audible and visual alarm actions of the alarm device and the power-off action of the power switch; the information is wirelessly transmitted via the relay router, so that an underground condition can be effectively known and controlled via the upper computer of the ground control center.

A semiconductor storage apparatus having an SRAM memory cell of a low power consumption type which can reduce a wiring length of a bit line. NMOS transistors N1, N3 and N4 are formed in a P well region PW0, NMOS transistors N2, N5 and N6 are formed in a P well region PW1 and a wiring direction (a second direction) of bit lines BL1 and BL2 (bit lines BL12 and BL22) is set to be orthogonal to a direction of separation arrangement (a transverse direction in the drawing; a first direction) of the P well regions PW0 and PW1. The P well region PW0 and the P well region PW1 are formed opposite to each other with an N well region interposed therebetween.

The invention relates to an intelligent monitoring system for a wind power blade assembly mold. The intelligent monitoring system comprises a sensor, a signal acquisition and transmission system and acontrol system; the sensor comprise a plurality of vacuum degree sensors, a temperature sensor and a plurality of laser displacement sensors, and the laser displacement sensors are used for detectingthe width of a mold closing joint and the axial and chordwise dislocation degree of the mold closing joint; the multiple vacuum degree sensors are respectively installed on vacuumizing pipelines at the rear edge of an upper mold and the rear edge of a lower mold; the temperature sensor comprises a plurality of thermal resistors pre-buried in the surfaces of the upper mold and the lower mold, andthe thermal resistors are uniformly distributed on the whole surfaces of the upper mold and the lower mold; and the upper mold and the lower mold are divided into a plurality of areas, each area is provided with a data acquisition module, each data acquisition module is used for acquiring sensor data of the area nearby and sending the sensor data to an upper computer of the control system, and theupper computer monitors and displays the sensor data in real time. Parameters of the molds are fed back comprehensively, centrally and online, and the production efficiency and the product quality are improved.

The invention relates to an X-structure Steiner tree construction method considering a voltage conversion rate. The method comprises the following steps: S1) generating an initial Steiner tree structure; s2) pre-processing and memorizing information between the pin and the obstacle; s3) optimizing the Steiner tree structure by adopting a discrete particle swarm optimization algorithm, and obtaining the optimized Steiner tree structure through a particle updating process including speed updating, self-sensing and group sensing; s4) locally optimizing the Steiner tree structure to optimize the local structure of the Steiner tree structure so as to further shorten the wiring length; and S5) adjusting the constraint violating part in the Steiner tree structure through a hybrid correction strategy, so that the Steiner tree meets the voltage conversion rate constraint, and the final Steiner tree structure is obtained.The method is beneficial to optimizing the wiring length while meeting thevoltage conversion rate constraint.

The invention provides a semiconductor packaging structure, which comprises a substrate, a first chip, a first lead, a second adhesion layer, a second chip, a second lead, a first packaging body, a second packaging body and a conducting element, wherein the substrate is provided with a front and a back, and is also provided with an opening penetrating the substrate; the first chip is provided withan active surface and a back, covers the opening through a first adhesion layer in a mode that the active surface is upwards, and is attached to the back of the substrate through the first adhesion layer; the first lead is electrically connected with the first chip and the front of the substrate through the opening; the second adhesion layer coats the first lead and covers a solder pad on the active surface of the first chip and partial front of the substrate; the second chip is provided with an active surface and a back, the back of the second chip is downwards and the active surface is upwards relative to the first chip, and the second chip is attached to the front of the substrate through the second adhesion layer; the second lead is electrically connected with the active surface of the second chip and the front of the substrate; the first packaging body coats the first chip, the first adhesion layer, the first lead and partial back of the substrate; the second packaging body coststhe second chip, the second adhesion layer, the second lead and the partial front of the substrate; and the conducting element is arranged on the back of the substrate.

The invention relates to a heterogeneous layout legalization method considering a carry chain and position constraint. The method comprises the following steps: clustering a group of relative blocks into a virtual macro; finding an ideal position for the virtual macro, and defining one-to-many matching of a bipartite graph to represent a corresponding relationship between one macro and a plurality of discrete positions; dividing a carry chain through a clock region and position constraint; dividing a possible area into half columns of clock areas to enable the half columns of clock areas to meet clock constraints; constructing matching between a chain and a site, distributing the chain to a column, and relaxing an original problem into a binary linear programming problem; refining the inter-column chain, wherein each chain is uniformly distributed on the column according to the moving distance and the total density distribution; expanding the Abacus to develop a linkage legalization program; dividing the area into equal windows, so that the algorithm efficiency is improved. The method is beneficial to optimizing the legalization result of the digital circuit.

A converter with a DC link for converting an input voltage into an alternating voltage with a pre-determined amplitude and frequency for driving a single or multiple-phase load may include a number of modules which are stackable over one another. Each module may have a ceramic cooling body with a receiving surface on which electronic components of one phase are mounted, wherein the ceramic cooling body has channel(s) in the region of the receiving surface for carrying a coolant during the operation of the converter The converter may include a DC link capacitor and input-side and output-side power connections arranged on a first carrier having a arranged perpendicular to the receiving surface. The converter may also include a control unit for driving the electronic components of the phase, the control unit being arranged on a second carrier having a main plane arranged perpendicularly to the plane of the receiving surface.

The invention discloses a submersible pump system and a submersible pump, wherein the submersible pump comprises a protection housing (1), a pump body (2) arranged inside the protection housing (1), a motor (3) and a control device (4). The output shaft (31) of the motor (3) is connected with the pump body (2). The submersible pump further comprises a sealing mechanism (5) coated on the control device (4) to seal the control device (4) and a heat radiating system (6) for radiating the heat of the control device (4) outwards. The control device (4) of the submersible pump radiates heat through the heat radiating system (6) via the sealing mechanism (5) and the protection housing (1), which ensures the waterproof function to the control device (4) but also enables the heat from the electric components of the control device in the sealing mechanism to be released in water, achieving the heat radiating effect of the electric components. In addition, the submersible pump of the submersible pump system is connected in parallel, and a host machine is connected electrically in parallel with the submersible pump control signals in the system through a main line and through a power supply line, power supply can be provided. This reduces the wiring length of the control line and the power supply line, saving materials.