Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit

A technology of standard cell and layout method, applied in semiconductor devices, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of indeterminate gate electrode distance, inability to handle OPC, etc., and achieve the effect of reducing chip area and improving accuracy

Inactive Publication Date: 2006-06-28
SOCIONEXT INC
View PDF1 Cites 20 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this case, although the distance from the cell boundary of each standard cell to the gate electrode of the closest neighborhood in the cell is set constant, the distance from the cell boundary to the gate electrode of the closest neighborhood is Uncertain
Therefore, OPC cannot be processed in every standard cell

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit
  • Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit
  • Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0077] figure 1 is a layout of a standard cell according to Embodiment 1 of the present invention. The direction along the power supply wiring S of the standard cell refers to the X direction, and the direction perpendicular to the power supply wiring S refers to the Y direction. The power wiring S is only an example, and does not necessarily have to be configured as shown.

[0078] see figure 1 Reference numerals in , x1-x13 represent the wiring grid used in automatic placement & routing and provided along the X direction, y1-y8 represent the wiring grid provided along the Y direction, C1, C2 and C3 represent Standard cells, O1, O2 and O3 represent the starting point of C1, C2 and C3 respectively, T represents the terminal capable of transmitting the input signal or output signal of the standard cell Ci (i=1, 2, . . . ), and G represents the gate electrode.

[0079] Automatic place & route tools are automated design tools for locating cells and blocks and routing paths t...

Embodiment 2

[0091] Figure 5 It is a design flowchart of the automatic place & route method using standard cells according to Embodiment 2 of the present invention.

[0092] An automatic placement & routing apparatus for performing an automatic placement & routing method, comprising a connection information input device for obtaining connection information of a logic circuit from outside, a design constraint input device for obtaining design constraints of a logic circuit from outside, A layout information input device for externally obtaining standard cell layout information, a temporary layout device for temporarily arranging individual cells based on the obtained connection information, and a relocation for relocating temporarily arranged cells to reduce the area equipment. The automatic place & route apparatus of such a structure places and routes a logic circuit including a plurality of standard cells.

[0093] First, circuit connection information of logic circuits for connecting ...

Embodiment 3

[0101] Figure 7 It is a design flowchart of the automatic place & route method using standard cells according to Embodiment 3 of the present invention.

[0102] An automatic place & route apparatus for performing an automatic place & route method includes a connection information input device for externally obtaining connection information of a logic circuit, a design constraint input device for externally obtaining a design constraint of the logic circuit, Layout information input equipment for obtaining standard cell layout information from outside, layout equipment for arranging cells based on the obtained connection information, temporary wiring processing equipment for providing temporary wiring for terminals connecting individual cells, for forming terminals terminal forming processing equipment, and actual wiring processing equipment.

[0103] First, circuit connection information of logic circuits for connecting a plurality of standard cells to each other, design con...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on routing grids lined in a Y direction which is a direction vertical to a power-supply wiring of the cell used in automatic placement & routing and has a shape extended in an X direction which is a direction in parallel with the power-supply wiring, more specifically such a shape that, for example, a longer-side dimension of the terminal is equal to ''a routing grid interval in the X direction+a wiring width. According to the constitution, a cell area is reduced, which advantageously leads to the reduction of a chip area.

Description

technical field [0001] The invention relates to a standard unit, a standard unit library and a layout method of the standard unit for higher integration and reduced area. Background technique [0002] In LSI layout design using automatic place & route (place and route) tools with grid design schemes, cell terminals for input / output signal communication must be located at the intersection of the wiring grid along the X and Y directions place. In order to meet this requirement, it is necessary to set the height of the unit to an integer multiple of the interval between the wiring grids arranged along the Y direction, and set the width of the unit to an integer multiple of the interval between the wiring grids arranged along the X direction times. Also, when elements are placed next to each other without gaps, terminals may not be located at grid intersections. The X direction indicates the direction along the power supply wiring of the standard cell, and the Y direction ind...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L27/118H01L21/82G06F17/50
Inventor 一柳美和森胁俊幸当房哲朗
Owner SOCIONEXT INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com