Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Chip buried-in modularize structure

A modular and chip technology, applied in electrical components, electro-solid devices, circuits, etc., can solve the problems of unformed multi-functional module structure, time-consuming production and cost, single semiconductor chip, etc., which is conducive to mass production, The effect of saving process time and shortening wiring length

Active Publication Date: 2009-08-05
PHOENIX PRECISION TECH CORP
View PDF4 Cites 18 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] Although the above-mentioned packaging structure improves the packaging density and electrical functions of the chip, most of the embedded semiconductor chips are single-form components, and a multi-functional module structure has not yet been formed. Moreover, if it is applied to multiple chips, the manufacturing process It is still necessary to separately provide electrical connections for each of the multiple chips, which consumes production time and cost, and is not conducive to mass production

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Chip buried-in modularize structure
  • Chip buried-in modularize structure
  • Chip buried-in modularize structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0024] see figure 2 , which is a schematic cross-sectional view of Embodiment 1 of the chip-embedded modular structure of the present invention. As shown in the figure, the modular structure embedded in the chip includes: a first dielectric layer 20; semiconductor chips 21a, 21b, connected on the first dielectric layer 20, and formed on the semiconductor chips 21a, 21b A plurality of electrical connection pads 210a, 210b; the second dielectric layer 23, pressed or coated on the first dielectric layer 20, so that the semiconductor chips 21a, 21b are embedded in the first dielectric layer 20 and the Between the second dielectric layer 23; and the circuit structure 24, formed on the second dielectric layer 23, and the circuit structure 24 is formed in the second dielectric layer 23 through a plurality of conductive structures 241 (can be For example, conductive blind holes or bumps, etc.), are electrically connected to the electrical connection pads 210a, 210b on the semiconduc...

Embodiment 2

[0031] see image 3 , which is a schematic cross-sectional view of Embodiment 2 of the chip-embedded modular structure of the present invention. The structure is substantially the same as that of Embodiment 1 of the present invention, and only the differences will be described below. As shown in the figure, the main difference between Embodiment 2 and Embodiment 1 is that there is a core layer 32 between the first dielectric layer 30 and the second dielectric layer 33, and a through hole 320 is formed in the core layer 32. , 322, for semiconductor chips 31a, 31b to be accommodated in the openings 320, 322, when the second dielectric layer 33 is laminated or coated on the first dielectric layer 30 with the core layer 32 separated, the first And the second dielectric layer 30, 33 can be filled in these openings 320, 322, and these semiconductor chips 31a, 31b are embedded in their corresponding openings, and can be formed on the second dielectric layer 33 The circuit structure...

Embodiment 3

[0033] see Figure 4 , which is a schematic cross-sectional view of Embodiment 3 of the present invention. As shown in the figure, the embedded modular structure of the chip includes: a first dielectric layer 40; semiconductor chips 41a, 41b, connected to the first dielectric layer 40 and a plurality of electrical connection pads 410a, 410b are formed on the semiconductor chips 41a, 41b; the second dielectric layer 43 is pressed or coated on the first dielectric layer 40, so that the semiconductor chips 41a, 41b Buried between the first and second dielectric layers 40, 43; the wiring structure 44 is formed on the second dielectric layer 43, and the wiring structure 44 is electrically connected to the wiring structure 441 through a plurality of conductive structures electrical connection pads 410a, 410b of semiconductor chips 41a, 41b; circuit structure 45, formed on the outer surface of the first dielectric layer 40; and conductive vias 46, penetrating through the first and se...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

This invention relates to one chip imbed module structure ,which comprises dielectric layer, at least one layer of semiconductor chip and at least one circuit structure, wherein, the structure is connected to semiconductor slice through several conductive structures; backward module structure is imbedded into electron device through dielectric layer circuit structure and electron devices. The invention chip module structure applies each electron device process to make the circuit structure connected to electron device through each conductor.

Description

technical field [0001] The invention relates to a chip-embedded modular structure, in particular to a modular structure integrating at least one semiconductor chip. Background technique [0002] With the vigorous development of the electronic industry, electronic products are also developing in the direction of lightness, thinness, shortness, smallness, high integration and multi-function. In order to meet the high integration (Integration) and miniaturization (Miniaturization) packaging requirements of semiconductor packages, the package shape of semiconductor chips has gradually changed from a single chip ball grid array (BGA) package or flip chip (Flip Chip, FC) package. Evolving into 3D packaging and modular packaging forms, resulting in different packaging structures, such as SiP (System in Package), SIP (System Integrated Package), SiB (System in Board) and other forms. [0003] These 3D and modular packaging forms use flip chip technology (flip chip) or wire bonding ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L23/488
CPCH01L2924/15311H01L2224/73204H01L2224/16225H01L24/18H01L2224/32225H01L2224/04105H01L2224/12105H01L2224/16227H01L2224/19H01L2224/73267H01L2224/92244H01L2924/15153H01L2924/19105H01L2924/00H01L2224/18H01L2924/00012
Inventor 许诗滨
Owner PHOENIX PRECISION TECH CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com