Semiconductor momory

Abstract

A semiconductor storage apparatus having an SRAM memory cell of a low power consumption type which can reduce a wiring length of a bit line. NMOS transistors N1, N3 and N4 are formed in a P well region PW0, NMOS transistors N2, N5 and N6 are formed in a P well region PW1 and a wiring direction (a second direction) of bit lines BL1 and BL2 (bit lines BL12 and BL22) is set to be orthogonal to a direction of separation arrangement (a transverse direction in the drawing; a first direction) of the P well regions PW0 and PW1. The P well region PW0 and the P well region PW1 are formed opposite to each other with an N well region interposed therebetween.

Description

technical field [0001] The present invention relates to a memory cell structure of a semiconductor memory device having a SRAM (Static RAM) memory cell. Background technique [0002] In recent years, with the lightness, thinness, and miniaturization of electronic instruments, it is strongly required to realize the functions of these devices at high speed. It is indispensable to mount a microcomputer in such an electronic device, and it is necessary to incorporate a large-capacity and high-speed memory in the structure of the microcomputer. In addition, in addition to the rapid spread and high performance of computers, in order to realize higher-speed processing, it is required to increase the capacity of the cache memory. That is, RAM used when the CPU executes a control program or the like is required to be rigid and increase in capacity. [0003] As RAM, DRAM (Dynamic RAM) and SRAM are generally used, and SRAM is generally used for a part requiring high-speed processing ...

AI Technical Summary

Problems solved by technology

In addition, although the "memory cell" disclosed in the above-mentioned Japanese Unexamined Publication No. 07-7-89 is a design scheme of a 2-port SRAM unit, what is provided is that there is no major change to the design scheme of a single-port SRAM unit and can be easily The design scheme of adding the second port is not to shrink the 2-port SRAM cell in the direction of the bit line

[0019] Similarly, low power consumption type SRAM memory cells such as low power consumption type SRAM memory cells such as SRAM memory cells with a low power consumption type 8 transistor structure that will be shrunk to the flow selection signal line in the column direction from the memory cell selected by the word line as the row selection signal line have not been found. A specific solution to shorten the wiring length of the bit line

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