Clock legalization method based on heterogeneous FPGA layout

Abstract

The invention relates to a clock legalization method based on heterogeneous FPGA layout. The method comprises the following steps: (1) establishing a clock constrained mathematical model; and (2) based on the established mathematical model, carrying out clock constraint legalization in two steps of clock net contraction and clock net expansion. The method is beneficial to legalization of the clock, and prevents the clock line network from violating the clock constraint in the layout process.

Description

technical field [0001] The invention belongs to the technical field of VLSI physical design automation, and in particular relates to a clock legalization method based on heterogeneous FPGA layout. Background technique [0002] Heterogeneous Field Programmable Gate Array (FPGA) is currently a popular FPGA chip because it can realize multiple functions, has higher performance, and can meet various demands. Correspondingly, its design complexity and scale are also increasing, which brings great challenges to heterogeneous FPGA layout. [0003] The optimization goal of FPGA layout is usually line length, and routability, timing and power consumption will be considered at the same time. In current FPGA designs, there may be hundreds of global clocks. Due to the limited clock routing resources of the current FPGA chip, we need to consider the position of the clock net in the layout phase to avoid the failure of the clock net routing in the routing phase. [0004] The FPGA chip ...

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Problems solved by technology

Relatively, its design complexity and scale are also increasing, which brings great challenges to heterogeneous FPGA layout

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