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Resistive memory cell and related array structure thereof

A technology of resistive memory and array structure, applied in the field of array structure

Pending Publication Date: 2021-08-13
EMEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

At this time, the crack 108 in the insulating layer 104 will go through a redox process, so that the crack 108 is hardly connected between the upper electrode 102 and the lower electrode 106.

Method used

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  • Resistive memory cell and related array structure thereof
  • Resistive memory cell and related array structure thereof
  • Resistive memory cell and related array structure thereof

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Experimental program
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Embodiment Construction

[0034] Please refer to Figure 2A to Figure 2E , which shows the flow chart, top view and equivalent circuit of the manufacturing method of the resistive memory cell according to the first embodiment of the present invention.

[0035] Such as Figure 2A As shown, a plurality of gate structures 250, 260, 270 are formed above the surface of the P-well region PW, and each gate structure 250, 260, 270 has the same configuration. Furthermore, the gate structures 250 , 260 , 270 include insulating layers 252 , 262 , 272 and conductive layers 255 , 265 , 275 . Taking the second gate structure 260 as an example, the insulating layer 262 is located above the surface of the P-type well region PW, and the conductive layer 265 is located above the insulating layer 262 .

[0036] According to the first embodiment of the present invention, the insulating layer 262 is formed by stacking multiple material layers, and the conductive layer 265 is formed by stacking multiple material layers. ...

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Abstract

The invention relates to a resistive memory cell and a related array structure thereof. The resistive memory cell comprises a well region, a first doped region, a second doped region, a third doped region, a first gate structure, a second gate structure and a third gate structure. A first gate structure is formed over the surface of the well region between the first doped region and the second doped region. The second gate structure is formed over the second doped region. The third gate structure is formed over the surface of the well region between the second doped region and the third doped region. The first metal layer is connected to the first doped region and the third doped region. The second metal layer is connected to the conductive layer of the first gate structure and the conductive layer of the third gate structure.

Description

technical field [0001] The present invention relates to a memory cell of a non-volatile memory (Non-volatile memory), and in particular to a memory cell of a resistive random-access memory cell and its related array structure. Background technique [0002] A resistive random-access memory (ReRAM for short) is a non-volatile memory (non-volatile memory), which is composed of a plurality of resistive memory cells (ReRAM cells). Since resistive memory has fewer process steps and has a faster writing speed, resistive memory is very suitable to replace embedded flash memory in a system-on-chip (SOC). Therefore, memory manufacturers and foundries have begun to invest in the development and research of resistive memory. [0003] Please refer to figure 1 , which is shown as a known resistive memory cell. Such as figure 1 As shown, the resistive memory cell 100 includes a stacked bottom electrode 106 , insulating layer 104 , and top electrode 102 . After the resistive memory is ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/24H01L45/00G11C13/00
CPCG05F1/56G06N3/04G06N3/065H10B20/27H10B20/20Y02D10/00G06N3/063H01L23/5226H10B63/30H10N70/041H10N70/8833
Inventor 赖宗沐张纬宸陈学威
Owner EMEMORY TECH INC