Resistive memory cell and related array structure thereof
A technology of resistive memory and array structure, applied in the field of array structure
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[0034] Please refer to Figure 2A to Figure 2E , which shows the flow chart, top view and equivalent circuit of the manufacturing method of the resistive memory cell according to the first embodiment of the present invention.
[0035] Such as Figure 2A As shown, a plurality of gate structures 250, 260, 270 are formed above the surface of the P-well region PW, and each gate structure 250, 260, 270 has the same configuration. Furthermore, the gate structures 250 , 260 , 270 include insulating layers 252 , 262 , 272 and conductive layers 255 , 265 , 275 . Taking the second gate structure 260 as an example, the insulating layer 262 is located above the surface of the P-type well region PW, and the conductive layer 265 is located above the insulating layer 262 .
[0036] According to the first embodiment of the present invention, the insulating layer 262 is formed by stacking multiple material layers, and the conductive layer 265 is formed by stacking multiple material layers. ...
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