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Semiconductor package and method for manufacturing same

A technology for semiconductors and conductive pads, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems affecting the flow of electroless plating solutions, etc.

Pending Publication Date: 2021-09-03
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the spacer is a non-fixed configuration and thus may affect the flow of the electroless plating solution

Method used

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  • Semiconductor package and method for manufacturing same
  • Semiconductor package and method for manufacturing same
  • Semiconductor package and method for manufacturing same

Examples

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Embodiment Construction

[0024] Throughout the drawings and detailed description, common reference numbers are used to refer to the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0025] Such as "above", "below", "up", "left", "right", "down", "top", "bottom", "vertical", "horizontal", "side", " Higher", "lower", "upper", "above", "below" and other spatial descriptions are about a certain component or a certain group of components or a certain plane of a component or a group of components for the one or more specified by the orientation of each component, as shown in the associated drawings. It should be understood that the spatial descriptions used herein are for illustration purposes only, and that actual embodiments of the structures described herein may be spatially arranged in any orientation or manner, provided such arrangements do not depart from embodimen...

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PUM

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Abstract

Present disclosure provides a semiconductor package, including a first substrate having a first active surface and a first trench recessed from the first active surface, a second substrate having a second trench facing the first trench, and a pathway cavity defined by the first trench and the second trench. The first trench comprises a first metal protrusion and a first insulating protrusion. A method for manufacturing the semiconductor package described herein is also disclosed.

Description

technical field [0001] The present disclosure relates to a semiconductor package having a pathway cavity that allows fluid to pass therethrough and a method for manufacturing such a semiconductor package. Background technique [0002] Conventional chip-chip bonding, module-module bonding, chip-wafer bonding, chip-substrate bonding, and wafer-wafer bonding require the formation of metal bonds. Certain types of chips or modules, wafers, or substrates containing such chips may require low-temperature bonding operations to prevent performance degradation of such chips. In low temperature bonding operations, electroless Cu-Cu bonding may be an option. [0003] Current electroless Cu-Cu bonding employs a non-fixed spacer between opposing bonding surfaces in order to create a path for the electroless plating solution. However, the spacer is a non-fixed configuration and thus may affect the flow of the electroless plating solution. Furthermore, with the ever-increasing demands on...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31H01L23/16H01L21/56
CPCH01L23/3121H01L23/315H01L23/16H01L21/561H01L25/50H01L2224/95H01L2224/82007H01L2224/82138H01L2224/82101H01L2224/82365H01L2224/24105H01L2224/24145H01L2224/24991H01L2224/25112H01L24/95H01L24/82H01L24/24H01L24/25H01L2224/82H01L24/81H01L24/16H01L24/17H01L24/03H01L2224/81007H01L2224/81232H01L2224/03827H01L2224/16148H01L2224/10145H01L2224/16014H01L2224/17106H01L2224/11462H01L2224/11827H01L2224/16057
Inventor 洪筠净林咏胜高金利
Owner ADVANCED SEMICON ENG INC