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Branch prediction method, microprocessor thereof and data processing system

A microprocessor and branch technology, applied in electrical digital data processing, memory systems, instruments, etc., can solve the problems of increasing chip area, increasing access time, increasing BTB power, etc.

Inactive Publication Date: 2021-12-07
ANDES TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, increasing the size of the BTB results in increased chip area, increased access time, and increased power required for BTB operation

Method used

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  • Branch prediction method, microprocessor thereof and data processing system
  • Branch prediction method, microprocessor thereof and data processing system
  • Branch prediction method, microprocessor thereof and data processing system

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Embodiment Construction

[0059] The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these components and arrangements are examples only and are not intended to be limiting. For example, in the following description, the superimposition of two features may include an embodiment in which the two features are formed by direct contact, or an embodiment in which the two features may be superimposed through additional features without direct contact. Additionally, this disclosure may repeat reference numbers and / or letters in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0060] The function of the branch target buffer (BTB) is to perform branch prediction when fetching instructions. ...

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Abstract

A branch prediction method, a microprocessor thereof and a data processing system are provided. Translation look-aside buffer entries have virtual page addresses. Branch target buffer entries include location information representing the translation look-aside buffer entries that map the branch addresses and a target address. To perform a branch prediction, a branch target buffer and a translation look-aside buffer are accessed, wherein the position information representing one of the N entries in the translation look-aside buffer is used to determine whether to hit the branch target buffer; if yes, the branch target address of the branch address may be obtained by accessing the TLB using the position information of the target address in the branch target buffer, or when the same page in the hit branch target buffer entry is set, the branch page address is utilized to construct the branch target address corresponding to the branch address.

Description

technical field [0001] The present disclosure relates generally to microprocessors, and more particularly to methods of branch prediction and microprocessors and data processing systems therefor. Background technique [0002] Within a data processing system, a branch target buffer (BTB) is commonly used to predict the result of a branch instruction and the target address of the branch instruction in order to enhance performance. As microprocessors increase performance by increasing the number of pipeline stages and executing instructions in parallel, the size of the branch target buffer (BTB) is usually increased to improve hit rates and reduce branch mispredictions resulting performance loss. In addition, 4GB of data memory is no longer enough to handle large amounts of data from the Internet, so most high-end microprocessors require 64-bit memory addresses instead of the 32-bit memory addresses of 10 years ago. However, increasing the size of the BTB results in increased...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
CPCG06F9/3806G06F12/0864G06F2212/452G06F2212/684G06F2212/681G06F12/0875G06F2212/652G06F2212/1016G06F12/1027G06F2212/6082G06F9/3844G06F2212/68
Inventor 陈丁明
Owner ANDES TECH
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