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Non-blocking L1 Cache in multi-core SOC

A non-blocking, multi-core technology used in the field of computer architecture to solve problems such as the mismatch between the speed and bandwidth of processors and DRAM

Pending Publication Date: 2022-02-08
58TH RES INST OF CETC +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] For this reason, the technical problem to be solved by the present invention is to overcome the problem that the speed and bandwidth of the processor and DRAM do not match seriously in the prior art, thereby providing non-blocking L1 Cache in the multi-core SOC based on the RISCV instruction set

Method used

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  • Non-blocking L1 Cache in multi-core SOC
  • Non-blocking L1 Cache in multi-core SOC

Examples

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Embodiment Construction

[0032] This embodiment provides a non-blocking L1 Cache in a multi-core SOC. The L1 Cache includes two circuit modules, ICache and DCache. The ICache circuit module is designed as an 8-way set-associated dual-bank SRAM to provide data access for the CPU instruction fetching stage, specifically including:

[0033] Accept the request of the instruction fetch stage in the CPU pipeline;

[0034] Divide the 11-6 bits of the requested address into the 31-12 bits of the idx address and divide them into bit tags, idx is used to index the corresponding group number, and tag is used to compare whether they match;

[0035] Take out the corresponding effective bit and tag through idx. If the effective bit is valid, compare whether the eight tags match the tag requested by the CPU. If they match, it will judge the hit and return the corresponding data; if they do not match, report missing;

[0036] The missing data requested by the CPU will request the missing data from the bus;

[0037] ...

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Abstract

The invention relates to a non-blocking L1 Cache in a multi-core SOC (system on chip), the L1 Cache comprises an ICache circuit module and a DCache circuit module, the ICache circuit module is designed to be an eight-path-group-connected double-bank SRAM (static random access memory) for providing data access for a CPU (central processing unit) fetch stage, and the DCache circuit module is designed to be an eight-path-group-connected single-bank SRAM for providing data access for a CPU LSU (local switching unit) fetch stage; a control circuit and an assembly line in the ICache are designed; a control circuit, a pipeline, a replacement algorithm, a missing cache queue (MSHR) and a consistency protocol in the DCache are arranged. According to the non-blocking L1 Cache in the multi-core SOC disclosed by the invention, the problems of low access efficiency, difficulty in design and the like of the Cache in the existing multi-core SOC are solved.

Description

technical field [0001] The present invention relates to the technical field of computer architecture, in particular to a non-blocking L1 Cache in a multi-core SOC. Background technique [0002] With the development of semiconductor technology, the performance of memory is far behind the development of processors. From the early 1980s to the beginning of the 21st century, processors developed rapidly at a rate of about 50% per year, while DRAM performance increased by only 10 per year. % or so, the speed and bandwidth of the processor and DRAM seriously do not match, and frequent access to DRAM will occupy a large amount of bus bandwidth. The principle of locality in computer programs states that if a particular location of memory is accessed at a certain point, it is likely that the same location will be accessed again in the near future; Future access to nearby storage locations. Therefore, in a general-purpose processor CPU, a small and fast cache is often used to cache ...

Claims

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Application Information

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IPC IPC(8): G06F12/0877G06F12/0893
CPCG06F12/0877G06F12/0893
Inventor 魏敬和刘德莫海
Owner 58TH RES INST OF CETC
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