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Time sequence adjusting method and time-invariant computer readable medium

A timing and computer technology, applied in the direction of measuring electricity, measuring electrical variables, electrical digital data processing, etc., can solve the problems of unpredictable number of repeated executions, low, time-consuming efficiency, etc.

Pending Publication Date: 2022-03-01
SILICON MOTION INC (CN)
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the corresponding unit delay and the corresponding transfer delay are usually manually reduced and repeated an unpredictable number of times, resulting in time-consuming operations and inefficiencies

Method used

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  • Time sequence adjusting method and time-invariant computer readable medium
  • Time sequence adjusting method and time-invariant computer readable medium
  • Time sequence adjusting method and time-invariant computer readable medium

Examples

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Embodiment Construction

[0038] The following descriptions are examples of the present invention. Its purpose is to illustrate the general principles of the present invention and should not be regarded as a limitation of the present invention. The scope of the present invention should be defined by the scope of the patent application.

[0039] It can be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components , regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or parts. Therefore, a first element discussed below, A component, region, layer, and / or section could be termed a second element, component, region, layer, and / or section without departing from the teachings of some embodiments of the present disclosure.

[0040] It should be noted that the followin...

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PUM

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Abstract

The invention relates to a time sequence adjusting method and a non-time-varying computer readable medium, which are used for adjusting transmission delay of each path of an integrated circuit. The time sequence adjusting method comprises the following steps: in a worst mode, judging whether the transmission delay of a selected path exceeds a time sequence requirement or not; in the path mode, judging whether the transmission delay of the selected path exceeds a time sequence requirement or not; and reducing the cell delay of the worst mode of each cell in the selected path when the selected path does not exceed the timing requirement in the path mode.

Description

technical field [0001] The present invention relates to a method for eliminating fake faults in gate-level simulation (gate-level simulation) and shortening the design process. Background technique [0002] In the automated design of integrated circuits, static timing analysis (STA) is used to check the propagation delay of each path in the integrated circuit. In traditional static timing analysis, timing signoff (timing signoff) is used to correctly determine the propagation delay of each path in the integrated circuit, and then use the results of timing signoff to determine the gate level simulation of each path The maximum value and the minimum value of the cell delay of each cell (referred to as "worst mode" in the following paragraphs). [0003] When it is determined that the integrated circuit does not meet the timing requirements in the gate level simulation, it is determined whether any false errors have occurred in the integrated circuit. When it is determined tha...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/3315
CPCG06F30/3315G06F30/3308G01R31/31937G01R31/31725
Inventor 白家诚
Owner SILICON MOTION INC (CN)