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Signal edge detection delay circuit

A delay circuit and edge detection technology, applied in delayed output pulse operation, electrical components, pulse processing, etc., can solve the problems of complex signal edge detection circuit circuit and high hardware cost, and achieve the effect of simple structure and reduced hardware cost.

Active Publication Date: 2022-03-29
成都芯翼科技有限公司
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  • Application Information

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Problems solved by technology

[0003] The purpose of the present invention is to provide a signal edge detection delay circuit, which is used to solve the technical problems of complex signal edge detection circuit and high hardware cost in the prior art

Method used

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Embodiment

[0042] In order to solve the technical problems that the edge detection circuit structure existing in the prior art requires at least two stages of D flip-flops and multiple logic gates, and more than 40 transistors, the circuit structure is very complicated, and the hardware cost is high, the embodiment of the present application A signal edge detection delay circuit is provided, the circuit can realize the edge detection function through a simple circuit structure, and can be applied to the EEPROM of the SPI interface to realize the edge detection of the EEPROM.

[0043] to combine Figure 2-Figure 13 As shown, the present invention provides a signal edge detection delay circuit, including an edge selection unit, a delay unit and an output unit;

[0044] The input end of the edge selection unit is connected to a digital input signal, the output end of the edge selection unit is connected to the input end of the delay unit, the output end of the delay unit is connected to the...

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Abstract

The invention discloses a signal edge detection delay circuit. The signal edge detection delay circuit comprises an edge selection unit, a delay unit and an output unit, the edge selection unit is used for selecting to apply a rising edge or a falling edge to the digital input signal, generating a rising edge signal or a falling edge signal, and sending the rising edge signal or the falling edge signal to the delay unit; the delay unit is used for adding delay to the rising edge signal or the falling edge signal, generating an edge detection signal and sending the edge detection signal to the output unit; the output unit is used for receiving and outputting the edge detection signal. According to the invention, the edge detection function can be realized through a simple circuit structure, and the edge detection of the EEPROM can be realized; the depletion-type third NMOS tube MN03 is connected into a diode structure to control the transmission delay of a digital signal, and the diode structure effectively controls the discharge current, so that post-stage charges can be discharged to zero, an edge detection signal is generated, and the structure is simple.

Description

technical field [0001] The invention belongs to the technical field of electronic circuits, and in particular relates to a signal edge detection delay circuit. Background technique [0002] In the field of electronic circuit technology, signal edge detection is widely used. For example, in an EEPROM (Electrically Erasable Programmable readonly memory) of an SPI (Serial Peripheral Interface, Serial Peripheral Interface) interface, multiple edge detection circuits are required. like figure 1 , the figure shows the circuit structure in the prior art to realize signal edge detection in a digital way, the circuit structure requires at least two stages of D flip-flops and multiple logic gates, and more than 40 transistors are needed at the same time, the circuit structure is very complicated, Hardware costs are higher. Contents of the invention [0003] The purpose of the present invention is to provide a signal edge detection delay circuit, which is used to solve the technic...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K5/1534
CPCH03K5/1534H03K2005/00293
Inventor 洪锋明
Owner 成都芯翼科技有限公司
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