Write strategy adjustment method for cache, cache device and computing equipment

A technology for adjusting methods and strategies, which is applied in computing, memory systems, instruments, etc., can solve the problems of adverse effects of caching functions, friendly access scenarios that cannot be cached, etc., and achieve the effect of caching function optimization

Active Publication Date: 2022-04-08
摩尔线程智能科技(北京)有限责任公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004]About the cache write strategy, the processor generally can only choose a cache write strategy from the write-back strategy and the write-through strategy, but one strategy cannot be used for all caches The access scenarios are all friendly, and the caching function is thus adversely affected

Method used

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  • Write strategy adjustment method for cache, cache device and computing equipment
  • Write strategy adjustment method for cache, cache device and computing equipment
  • Write strategy adjustment method for cache, cache device and computing equipment

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Embodiment Construction

[0043] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure, and to fully convey the scope of the present disclosure to those skilled in the art.

[0044]In the description of the embodiments of the present application, it should be understood that terms such as "comprising" or "having" are intended to indicate the existence of the features, numbers, steps, acts, components, parts or combinations thereof disclosed in the specification, and do not It is intended to exclude the possibility of the existence of one or more other features, figures, steps, acts, parts, parts or comb...

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Abstract

The invention provides a write strategy adjusting method for a cache, a cache device and computing equipment, the cache comprises a plurality of cache groups mapped with a lower-level memory in a group associative mode, and the method comprises the following steps: setting a plurality of monitoring groups and a plurality of following groups in the plurality of cache groups, the monitoring groups comprise a first monitoring group configured to be in a write-back and write allocation mode and a second monitoring group configured to be in a direct write and non-write allocation mode; and monitoring instance modes executed by the first monitoring group and the second monitoring group in response to the cache access request, and adaptively adjusting a write strategy of the following group according to the instance modes. By means of the method, the write strategy can be adjusted in a self-adaptive mode according to the dynamically-changing cache access scene, and then the cache function is optimized.

Description

technical field [0001] The invention belongs to the field of caching, and in particular relates to a writing strategy adjustment method for caching, a caching device and a computing device. Background technique [0002] This section is intended to provide a background or context to embodiments of the invention that are recited in the claims. The descriptions herein are not admitted to be prior art by inclusion in this section. [0003] In order to improve system performance, modern processors (such as CPU, GPU, DPU, etc.) are generally designed with a cache (cache), or even a multi-level cache. Wherein the cache unit is configured to store a local copy of data accessed by the processor execution unit in memory, so that if access to those data is required again, re-access to the memory can be avoided by accessing the local copy stored in the cache The data. [0004] Regarding the write strategy of the cache, the processor generally can only choose one cache write strategy ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/0877G06F3/06
CPCY02D10/00
Inventor 李然月孟平凡刘杨时昊
Owner 摩尔线程智能科技(北京)有限责任公司
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