Implementation method and device for NVM subsystem reset, computer equipment and storage medium

Abstract

The invention relates to an implementation method and device for NVM subsystem reset, computer equipment and a storage medium. The method comprises the steps that an SSD obtains a subsystem reset interrupt signal sent by an SSD controller; the firmware jumps to an interrupt processing function to process the event, and judges whether the SSD has a command which is not completely processed or not; if the command is not completely processed, marking that the user reset mode event is not subjected to reset related operation; the interrupt processing function is quitted, and when the SSD returns to the main state machine and enters a restarting state, the ongoing command is terminated; all commands are normally terminated and completed; the firmware sends an LTSSM stopping request to the SSD controller, the SSD performs PCIe core resetting, the SSD waits for normal availability of a reference clock, the SSD reconfigures a PCIe register, the SSD performs NVMe core resetting, the SSD performs NVMe initialization, and the firmware sends an LTSSM starting request to the SSD controller. According to the invention, the purpose that different test platforms can pass tests can be achieved.

Description

technical field [0001] The invention relates to the technical field of solid-state hard drives, in particular to a method, device, computer equipment and storage medium for realizing NVM subsystem reset. Background technique [0002] Currently, NVM Subsystem reset (NVM Subsystem Reset) occurs in the following three situations: main power is applied to NVM Subsystem; 4E564D65h ("NVMe") is written to NSSR.NSSRC (NVM Subsystem Reset.NVM SubsystemReset Control Subsystem Reset Control ) field; when a special event defined by the manufacturer occurs, the NVM subsystem will reset (reset). When the NVM subsystem is reset, the entire NVM subsystem is reset, including a reset of all controller hierarchies that make up the NVM subsystem, disabling the persistent memory regions associated with all controllers that make up the NVM subsystem, and All PCIe ports of the system transition to detect LTSSM state. [0003] However, the existing Subsystem reset solution fails the reset test on...

AI Technical Summary

Problems solved by technology

[0003] However, the existing Subsystem reset solution failed the reset test on the sanblaze (a SSD test software) test platform

On this platform, because the SSD is reading and writing commands, the host sends a reset request before the end of the read and write commands. When the Device receives the reset interrupt, it resets the PCIe / NVMe Core (core) during the interrupt, resulting in unprocessed Node gets stuck, doesn't finish successfully, fails final test

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