A communication link update method, device and related equipment

Abstract

The application discloses a method for updating a communication link, which includes traversing the registers in the target communication link to determine the DownTrain register; setting a prohibition flag in the DownTrain register; reading the configuration information of each register in the target communication link, Generate a configuration file; use the configuration file to update each communication link. Apply the technical solution provided by this application, first find the DownTrain register in the target communication link, and set the prohibition flag bit for it, so that when the communication link is partially Lane Down (closed), the entire link is closed, so that The problem of inconsistency between sending and receiving data during data transmission is effectively avoided; further, batch updates of communication links can also be realized based on the configuration information of the modified registers. The present application also discloses a communication link updating device, equipment and computer-readable storage medium, all of which have the above beneficial effects.

Description

Technical field [0001] The present application relates to the field of communication technology, in particular to a communication link update method, but also to a communication link update device, equipment and computer-readable storage medium. Background [0002] In the field of storage, with the popularity of nvme SSDs (Solid State Drives, solid state drives), based on PCIe (peripheral component interconnect express, high-speed serial computer expansion bus standard) direct connection of the hard disk frame has also developed, the storage controller uses PCIe cable, generally for MiniSasHD (a connector) cable to connect the hard disk expansion cabinet, hard disk frame. [0003] In order to meet the performance requirements, the PCIe bandwidth between the controller and the expansion cabinet is generally more than x16, and the common MiniSas cable is x4, so it is often used to connect the controller and the expansion cabinet, because multiple cables are used, and each cable may...

AI Technical Summary

Problems solved by technology

[0004] As mentioned above, when the cable other than Lane0 is plugged or disconnected, PCIe LTSSM enters the Recover process, but the link is not declared closed, and the PCIe link layer will continue to resend the unrecovered message because it cannot get the ack from the peer. Confirm the message, and at this time there is a new data transmission request generated later, because the Tag uses 5 bits by default, it will be multiplexed in this scenario, that is, for the same BDF device (a PCIe device), the confirmation data is Which memory address is read and written depends on the Tag mark. If the mark is multiplexed, it will lead to read and write errors. For storage devices, data inconsistency is a problem, that is, after the CPU sends data, it is received on the SSD side. The receipt that arrived was misplaced

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