Simulation method and simulation system based on SPICE model

A simulation method and simulation system technology, applied in the field of simulation method and simulation system based on SPICE model, can solve the problem of taking up too many test resources and so on.

Pending Publication Date: 2022-04-29
深圳天狼芯半导体有限公司
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Problems solved by technology

[0004] The purpose of the present invention is to provide a simulation method and a simulation system based on a SPICE model, aiming to solve the problem of excessive test resource occupation in the current LDE test

Method used

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  • Simulation method and simulation system based on SPICE model
  • Simulation method and simulation system based on SPICE model
  • Simulation method and simulation system based on SPICE model

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Embodiment Construction

[0040] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0041] The embodiment of the present application also provides a simulation method based on a SPICE model, see figure 1 As shown, the simulation method includes steps S10 to S60.

[0042] In step S10, the device structure of the simulated device is established, and its electrical curve is simulated.

[0043] In this embodiment, by establishing the device structure that needs to be simulated, and simulating its electrical curve, the WAT result is obtained through subsequent Wafer Acceptance Test (WAT) definition.

[0044] In one embodiment, the electrical curve at least includes an IV curve and a ...

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Abstract

The invention belongs to the technical field of semiconductor simulation, and mainly provides a simulation method and a simulation system based on an SPICE model, and the method comprises the steps: building a device architecture of a simulation device, and simulating an electrical curve of the device architecture; defining a wafer acceptance test parameter of the simulation device, and performing an electrical test on the simulation device according to the electrical curve to obtain a first electrical parameter; obtaining electrical simulation data of a wafer acceptance test through simulation, and comparing the electrical simulation data with the first electrical parameter to obtain an LED input parameter and an electrical change parameter of the wafer acceptance test; performing neural network-like training based on the LDE input parameters and the electrical change parameters to obtain neural network-like weighting parameters and a neural network-like architecture; and writing the obtained neural network-like weighting parameters and the neural network-like architecture into a model card, thereby realizing simulation of the device based on the model card of the SPICE model, and avoiding the problem of large test workload caused by the fact that a user needs to write a function into the model card in the current LDE simulation.

Description

technical field [0001] The invention belongs to the technical field of semiconductor simulation, and in particular relates to a simulation method and a simulation system based on a SPICE model. Background technique [0002] Layout dependent effect (layout dependent effect, LDE) is an important phenomenon affecting the device, because the stress and electric field around the device will directly affect the performance of the device. In the simulation circuit simulator (Simulation Program Integrated Circuit Emphasis, SPICE), the model card (model card) must accurately describe the LDE phenomenon in order to achieve accurate S2S (SPICE to Silicon). [0003] The LDE simulation of the current SPICE model card usually draws all kinds of LDE effects that greatly affect the electrical effect and put them into the SPICE test pattern. However, this operation will make the LDE test area account for more than the SPICE-related test area. 50%, resulting in more than 50% of test resource...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/20G06N3/04
CPCG06F30/20G06N3/04
Inventor 曾健忠
Owner 深圳天狼芯半导体有限公司
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