Data processing system and chip based on multi-dimensional arbiter

Abstract

The invention relates to a data processing system and chip based on a multi-dimensional arbiter, the data processing system comprises the multi-dimensional arbiter and N output end FIFOs, each output end FIFO is used for storing input data of one data type, the multi-dimensional arbiter is connected with each output end FIFO, a plurality of pieces of priority information are configured in the multi-dimensional arbiter, and N is an integer greater than or equal to 1. Each piece of priority information corresponds to a state combination, the state combination is the state combination of N output end FIFOs, the states of the output end FIFOs comprise a full storage state and a non-full storage state, and the multiple pieces of priority information are mutually independent. According to the system, under the condition that the chip area is not increased, blockage of multiple input channels can be relieved, deadlock of the multiple input channels can be avoided, and the data processing efficiency of the chip is improved.

Description

technical field [0001] The invention relates to the field of chip technology, in particular to a data processing system and chip based on a multidimensional arbiter. Background technique [0002] In existing chips, there is usually a case of processing multi-channel input data. In the prior art, an arbiter is usually set to select one of the multiple input data and store it in the receiving end FIFO (First InputFirst Output, advanced First out queue) for subsequent processing. When the FIFO at the receiving end is full, it will cause multi-channel data congestion. If the receiving end sets multiple receiving end FIFOs to classify and store multi-channel data, although it can properly alleviate the congestion of multiple input data at the sending end, if an arbitrator is used, it is likely to cause some input channels to deadlock. Setting an arbiter for each FIFO at the receiving end will result in an excessively large chip area and increase chip power consumption. It can ...

AI Technical Summary

Problems solved by technology

When the FIFO at the receiving end is full, it will cause multi-channel data congestion

If the receiving end sets multiple receiving end FIFOs to classify and store multi-channel data, although it can properly alleviate the congestion of multiple input data at the sending end, if an arbitrator is used, it is likely to cause some input channels to deadlock. Setting an arbiter for each receiving FIFO will cause the chip area to be too large and increase the power consumption of the chip

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