Verification method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a verification method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining a first verification case; according to the first verification case, a corresponding verification environment is created, the verification environment is provided with a corresponding first parameter configuration tree, and the first parameter configuration tree at least comprises parameter nodes corresponding to all environment components; based on the verification environment and the corresponding first parameter configuration tree, the to-be-tested object is verified, a verification result of the to-be-tested object under the first verification case is obtained, and in the verification process, parameters needed by all the environment components in the verification environment are obtained from parameter nodes corresponding to all the environment components. According to the embodiment of the invention, the parameters of the verification environment are uniformly managed through the parameter configuration tree, and the parameters of the environment components of the verification environment are uniformly obtained from the corresponding parameter nodes, so that the parameters of the environment components are separated from the environment, the parameter readability and management efficiency are effectively improved, and the verification working efficiency is improved.

Description

technical field [0001] The present disclosure relates to chip technology, in particular to a verification method and device, electronic equipment and a storage medium. Background technique [0002] In the field of chip front-end verification, the configurable verification environment is one of the important means to improve the versatility of the verification environment. The verification environment is usually complicated in parameters and difficult to maintain. For this situation, the related technology usually defines the environment component in the environment component class. Parameters, for different verification use cases, need to re-modify the environment, resulting in poor readability of parameters, low management efficiency, resulting in low verification work efficiency. Contents of the invention [0003] In order to solve the above-mentioned technical problems, the present disclosure is proposed. Embodiments of the present disclosure provide a verification met...

AI Technical Summary

Problems solved by technology

[0002] In the field of chip front-end verification, the configurable verification environment is one of the important means to improve the versatility of the verification environment. The verification environment is usually complicated in parameters and difficult to maintain. For this situation, the related technology usually defines the environment component in the environment component class. Parameters, for different verification use cases, the environment needs to be re-modified, resulting in poor readability of parameters and low management efficiency, resulting in low verification work efficiency

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