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Transactions supporting interrupt destination redirection and level triggered interrupt semantics

A transaction and remote task technology, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of limiting the transmission interruption speed of the serial bus, slow APIC serial bus, etc.

Inactive Publication Date: 2005-11-02
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Difficulty switching between these disparate frequencies
Since the signals are independent of each other, this problem will be more prominent
[0009] Third, the APIC serial bus is slower
Limits the speed at which interrupts can be transmitted on the serial bus when using more I / O-intensive functions

Method used

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  • Transactions supporting interrupt destination redirection and level triggered interrupt semantics
  • Transactions supporting interrupt destination redirection and level triggered interrupt semantics
  • Transactions supporting interrupt destination redirection and level triggered interrupt semantics

Examples

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Embodiment Construction

[0028] Referring to FIG. 1 , a multiprocessor computer system 10 includes processors P0 , P1 , P2 and P3 connected by a processor bus 18 . In some embodiments, processor bus 18 is referred to as a front-side bus. The invention can be used in conjunction with systems having more or fewer than four processors. Processors P0, P1, P2, and P3 include interrupt control logic 22, 24, 26, and 28, respectively, that include a task priority flag that indicates the priority of the task that is interrupted. priority. As an example, the task priority may be an 8-digit number. Generally speaking, if the priority of an interrupt is lower than the value in the task priority register in the processor, the processor will not affect said interrupt.

[0029] Remote priority capture logic 32 contains task priority data representing the task priority of those of processors P0, P1, P2 and P3 available for lowest priority interrupt destination arbitration (LPIDA). For example, the task priority d...

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PUM

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Abstract

In one embodiment, the invention includes an apparatus, such as a bridge (104), for use with a computer system (100) having a processor bus (18). The apparatus includes decode logic (36) to receive through the processor bus a task priority update transaction including data representative of a task priority designation of a processor of the computer system, and to provide a signal responsive thereto. The apparatus also includes remote priority capture logic (32) to receive the signal responsive to the task priority update transaction and update contents of the remote priority capture logic in response thereto. In another embodiment, the invention includes an apparatus for use with a computer system having a processor bus. The apparatus includes decode logic to receive through the processor bus an end-of-interrupt (EOI) transactions and to provide an EOI signal responsive thereto. The apparatus also includes an interrupt controller including a table having a state bit that is set in response to the interrupt controller receiving an interrupt signal and reset in response to the interrupt controller receiving the EOI signal.

Description

technical field [0001] The present invention relates to a processor system, and more particularly, the present invention relates to a processor system including processors capable of providing task priority update transactions and interrupt end transactions on a processor bus. Background technique [0002] Processors such as the Pentium(R) processor and the Pentium(R) Pro processor produced by Intel Corporation are commonly used in multiprocessor systems. Various devices, including input and / or output (I / O) devices, and other processors can interrupt a processor. To interrupt a processor, the I / O devices provide signals to the interrupt controller, which in turn issues an interrupt request to the processor. [0003] In the case of the Pentium(R) processor and the Pentium(R) Pro processor, the interrupt controller communicates interrupt information to the processor through a three-wire serial bus called the APIC (Advanced Programmable Interrupt Controller) bus. The APIC ser...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/26
CPCG06F13/26
Inventor S·S·帕洛维斯基D·G·刘K·C·威尔
Owner INTEL CORP
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