Heat-dissipating gain-type conductor holder
A lead frame and wire technology, applied in the lead frame field, can solve problems such as difficulty in steps, and achieve the effect of improving direct heat dissipation and avoiding tilt or offset
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no. 1 Embodiment
[0026] see Figure 2a , Figure 2a It is a partial perspective view of the lead frame 10 of the present invention (for the sake of clarity, the symmetrical structure of another part of multiple pins is not shown in the figure), the lead frame 10 of the present invention is suitable for being arranged in a package body 11, The semiconductor chip 13 is electrically connected through the wire 12 , wherein the lead frame 10 includes: a chip holder 14 , a bottom pad 17 , at least one connecting portion 18 and a plurality of pins 19 .
[0027] see Figure 2b , Figure 2b In order to show the cross-section (along Figure 2a XX" line) schematic diagram of the lead frame 10, wherein the above-mentioned chip holder 14 is arranged in the above-mentioned package body 11, and has a first surface 15 and a second surface 16 opposite to the above-mentioned first surface 15, and the above-mentioned first surface 15 For placing the above-mentioned chip 13 (for example, using silver glue as ...
no. 2 Embodiment
[0032] see Figure 3a , Figure 3aIt is a partial perspective view of the lead frame 10 of the present invention (for the sake of clarity of description, the symmetrical structure of another part of multiple pins is not shown in the figure), the lead frame 10 of the present invention is suitable for being arranged in the package body 11, through The wire 12 is electrically connected to the semiconductor chip 13 , wherein the lead frame 10 includes: a chip holder 14 , two bottom pads 17 , at least one connecting portion 18 and a plurality of pins 19 .
[0033] see Figure 3b , Figure 3b In order to show the cross-section (along Figure 3a The XX" line of the lead frame 10) schematic diagram, the above-mentioned chip holder 14 is arranged in the above-mentioned package body 11, and has a first surface 15 and a second surface 16 opposite to the above-mentioned first surface 15, and the above-mentioned first surface 15 For placing the above-mentioned chip 13 (for example, usi...
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