Storage circuit with odd-even check unit array

Abstract

A storage circuit has: an actual cell array; a parity generation circuit for generating parity bits from data in the actual cell array; a parity cell array; a refresh control circuit for sequentially refreshing the actual cell array, and when the internal When a refresh request and a read request occur simultaneously, priority is given to a refresh operation; a data restoration part restores data read from an actual cell array according to a parity bit read from a parity cell array; and an output circuit for Output the data from the actual cell array. In addition, the memory circuit has a test control circuit that prohibits the refresh operation of the actual cell array in the first test mode to output data read from the actual cell array, and controls the output circuit in the second test mode to output data from the parity register. Test the data read out from the cell array.

Description

technical field [0001] The present invention relates to a memory circuit having a parity cell array, and more particularly, to a memory circuit capable of testing the actual cell array and the parity cell array. [0002] The present invention also relates to a semiconductor memory having a memory cell array for storing parity data of write data and having an internal self-test (BIST) function. Background technique [0003] A one-transistor type of dynamic RAM (DRAM), which is a low-cost, high-capacity memory, is widely used, but requires a refresh operation even in a power-on state due to its volatility. On the other hand, in the case of static RAM (SRAM), although the increase in capacity requires a higher cost, in the powered state, this kind of SRAM can continuously maintain the stored data, that is, it does not need to be used like DRAM. Controls the refresh operation. [0004] Conventionally, SRAM that does not require refresh control has been used in mobile phones, m...

AI Technical Summary

Problems solved by technology

[0007] However, with the above-mentioned DRAM, when reading the data of the actual cell array, the data of the actual cell array may sometimes be partially corrected by a parity bit read from the parity cell array

Therefore, there is a problem: it cannot be properly tested for operation before shipment

For this reason, using the traditional self-test technology, the test pattern generated by the test circuit cannot be directly provided to the data bus connected to the parity check cell array PCA

Therefore, it is not possible to test DRAM with parity cell array PCA by internal self-test

Images