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Microprocessor device capable of selectively withdraw prefetch and method

A microprocessor, selective technology, applied in electrical digital data processing, instruments, memory systems, etc., can solve problems such as unfavorable cache efficiency, being used or about to be used, etc., to reduce the possibility of unfavorableness and improve efficiency. Effect

Inactive Publication Date: 2007-07-18
IP FIRST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Unconditionally withdrawing an early prefetch cache line to its cache has the disadvantage that the recalled cache line may replace a cache line that is being used or is about to be used, thus possibly affecting the cache has an adverse effect on the efficiency of

Method used

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  • Microprocessor device capable of selectively withdraw prefetch and method
  • Microprocessor device capable of selectively withdraw prefetch and method
  • Microprocessor device capable of selectively withdraw prefetch and method

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Experimental program
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Embodiment Construction

[0035]Please refer to FIG. 1, which is a block diagram illustrating an apparatus within a microprocessor 100 for selectively retiring a majority of prefetch cache lines. The microprocessor 100 includes a plurality of stages coupled to each other to form a pipeline. One or more of the pipeline stages include an address generator for generating a memory access operation address, such as the load / store address 132 shown in FIG. 1 . The load / store address 132 specifies an address for a load or store operation. A load operation reads data from the memory to the microprocessor 100, and a store operation writes data from the microprocessor 100 to the memory. In one embodiment, the load / store address 132 is a physical memory address.

[0036] Microprocessor 100 also includes a cache 104, which includes an N-way set associative cache. In one embodiment, the cache 104 includes a 4-way set associative 64KB cache. In a specific embodiment, the cache 104 is a level-1 data cache; but th...

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PUM

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Abstract

An apparatus in a microprocessor for selectively retiring a prefetched cache line is disclosed. In a first embodiment, a first count of the number of accesses to the prefetched cache line and N second counts of the number of accesses to N lines of a replacement candidate set of the cache selected by the prefetched cache line address are maintained. When another prefetch is requested, if the first count is greater than the smaller of the N second counts, the candidate prefetched cache line is retired into the cache; otherwise the prefetched cache line is discarded. In a second embodiment, a count of accesses to the replacement candidate line is maintained. When another prefetch is requested, if the count is greater than a programmable threshold value, the candidate prefetched cache line is retired into the cache; otherwise the prefetched cache line is discarded.

Description

technical field [0001] The present invention relates to the field of cache, especially to the prefetching of cache lines, that is, to a microprocessor device that can selectively undo prefetching. Background technique [0002] Today's computer systems include a microprocessor and a system memory for storing instructions of the microprocessor and data processed by the instructions of the microprocessor. Generally speaking, the time required to read data from system memory will be much longer than the time required by the microprocessor to execute one or more instructions-in some cases, even ten or twenty times more, so , while loading data from system memory, the microprocessor is often idle, which is very inefficient and degrades system performance. [0003] In order to alleviate the impact of the above problems on the system, a high-speed cache is usually built in the microprocessor. This high-speed cache is built in the microprocessor, and its memory capacity is smaller t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/00G06F12/06G06F12/0862
CPCG06F12/0862G06F2212/6022
Inventor 罗德尼·E·胡克G·葛兰·亨利
Owner IP FIRST