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Message scheduling method and system for many-core network processor and its micro-engine

A technology of network processor and scheduling method, applied in transmission systems, digital transmission systems, data exchange networks, etc., can solve the problems of complex mapping, time-out retransmission, and difficulty in implementation.

Active Publication Date: 2020-02-07
SANECHIPS TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] Secondly, the mapping between packets and microengines is also a complex problem. There are many mapping algorithms proposed so far, but most of them can only improve one aspect or the algorithms are too complicated to be implemented on hardware. Among them, the packets between the same data flow have the locality of the upper layer application, and it is necessary to ensure the order of the packets entering and leaving the network processor as much as possible to avoid the timeout retransmission of the upper layer of the network

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  • Message scheduling method and system for many-core network processor and its micro-engine
  • Message scheduling method and system for many-core network processor and its micro-engine
  • Message scheduling method and system for many-core network processor and its micro-engine

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[0159] Although in the above description, the organizational structure of the micro-engine is fully parallel, another advantage of the present invention is that it can support a serial organizational structure at the same time. For a long time, among commercial network processors, the serial micro-engine structure is a mainstream architecture, which has the advantages of guaranteed performance and no disorder. The implementation examples of the serial structure of the present invention are as follows:

[0160] All messages come in from the first cluster. After being processed, the next-level processing cluster number is designated by microcode. After the message comes out of the first cluster, in the routing module, specify the next level of processing according to the microcode. The cluster number moves the message from to the next cluster, so that the message processing is completed after the message passes through all clusters. Such as Figure 7 Shown.

[0161] The present inv...

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Abstract

The invention discloses a message scheduling method and system for a many-core network processor and its micro-engine, comprising: when a message is input, applying for an idle pointer for the message; storing the message in a shared cache The position pointed to by the instruction in , and store the pointer in the corresponding flow queue, wherein, the round-robin scheduling method is used for scheduling between the flow queues; when the pointer in the flow queue is scheduled, the search for the The microengine corresponding to the pointer is mapped to the microengine corresponding to the pointer; when the microengine corresponding to the pointer is not found, the pointer is stored in the corresponding flow queue again.

Description

Technical field [0001] The invention relates to network processor technology, in particular to a message scheduling method and system for a many-core network processor and its micro-engine. Background technique [0002] The network processor is the core component of the forwarding plane in the data communication field. It is a solution that takes into account the speed and flexibility of the processor. It can flexibly modify the business microcode to meet the needs of various basic and complex network services. Business expansion and upgrade. [0003] Due to the rapid development of network services, the processing power requirements of network processors are becoming higher and higher, and a single or a small number of micro-engines are far from meeting the demand for processing power. The current solutions mainly include methods such as increasing the system clock speed and increasing the number of cores. The method of increasing the system's main frequency, the development spe...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/751H04L12/803H04L12/863H04L45/02
CPCH04L45/02H04L47/125H04L47/50
Inventor 袁力
Owner SANECHIPS TECH CO LTD