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Method for selective prefetch retire

A selective, prefetching technology, applied in the direction of memory address/allocation/relocation, instrumentation, calculation, etc., can solve the problems of being used or about to be used, unfavorable cache efficiency, etc., to reduce the unfavorable possibility and increase the The effect of efficiency

Inactive Publication Date: 2007-10-31
IP FIRST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Unconditionally withdrawing an early prefetch cache line to its cache has the disadvantage that the recalled cache line may replace a cache line that is being used or is about to be used, thus possibly affecting the cache has an adverse effect on the efficiency of

Method used

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  • Method for selective prefetch retire
  • Method for selective prefetch retire
  • Method for selective prefetch retire

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Experimental program
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Embodiment Construction

[0036] Please refer to FIG. 1, which is a block diagram illustrating an apparatus within a microprocessor 100 for selectively retiring a majority of prefetch cache lines. The microprocessor 100 includes a plurality of stages coupled to each other to form a pipeline. One or more of the pipeline stages include an address generator for generating a memory access operation address, such as the load / store address 132 shown in FIG. 1 . The load / store address 132 specifies an address for a load or store operation. A load operation reads data from the memory to the microprocessor 100, and a store operation writes data from the microprocessor 100 to the memory. In one embodiment, the load / store address 132 is a physical memory address.

[0037] Microprocessor 100 also includes a cache 104, which includes an N-way set associative cache. In one embodiment, the cache 104 includes a 4-way set associative 64KB cache. In a specific embodiment, the cache 104 is a level-1 data cache; but t...

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Abstract

The invention discloses a method which selectively retires a prefetched cache line to a cache of a microprocessor from a prefetch buffer. The steps of the method comprises: saving a first count for accessing the prefetched cache line; receiving a prefetched new cache line to the prefetch buffer; judging whether a second count for replacing storing cache line accessed in the cache smaller than the first count as a response for receiving the require; if the second count is smaller than the first count, rewriting the new cache line to the prefetched cache line of the prefetch buffer.

Description

[0001] This patent application is a divisional application of the patent application with the filing date of October 17, 2003, the application number of 200310101482.1, and the title of "Microprocessor Device and Method for Selective Revocation of Prefetch". technical field [0002] The present invention relates to the field of cache, especially to the prefetching of cache line, that is, to a microprocessor device and method that can selectively undo prefetching. Background technique [0003] Today's computer systems include a microprocessor and a system memory for storing instructions of the microprocessor and data processed by the instructions of the microprocessor. Generally speaking, the time required to read data from system memory will be much longer than the time required by the microprocessor to execute one or more instructions-in some cases, even ten or twenty times more, so , while loading data from system memory, the microprocessor is often idle, which is very ine...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/08G06F12/00G06F12/06G06F12/0862
CPCG06F12/0862G06F2212/6022
Inventor 罗德尼·E·胡克G·葛兰·亨利
Owner IP FIRST