Drive circuit of power semiconductor element
A technology of power semiconductors and drive circuits, which is applied to semiconductor devices, output power conversion devices, circuits, etc., and can solve problems such as longer time
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Embodiment 1
[0042] In order to suppress the occurrence of surge voltage, the present invention can adjust the gate voltage waveform when the current is cut off according to the current value flowing on the power semiconductor element. Therefore, in order to estimate the current value of the power semiconductor element, it is possible to detect the gate voltage (Miller voltage) of the semiconductor power element when it is turned off. The detection timing can also be adjusted with an input control signal through the sampling signal generating circuit.
[0043] figure 1 is a circuit diagram showing the configuration of a drive circuit for a power semiconductor element according to Embodiment 1 of the present invention. exist figure 1Among them, 100 is the main inverter circuit for on / off switching of the power semiconductor element; 7 is a sampling signal generating circuit that generates a sampling signal only when it is turned off with reference to the signal from the input control sign...
Embodiment 2
[0060] As an example of the configuration of the sampling signal generating circuit 7 of the first embodiment, there is a method using an ASIC. In this case, arbitrary waveforms can be generated. For example, when the input control signal 90 (solid line) indicated by the solid line in FIG. 5 is input to the driver, the gate voltage 91 becomes as shown by the dotted line in FIG. 5 . The circuit of the present invention can only work in shutdown, so the ASIC output Image 6 The waveform shown will do.
[0061] Also in this embodiment, the same effect as that of the first embodiment described above can be obtained.
Embodiment 3
[0063] Figure 7 An example of the sampling signal generating circuit 7 different from that of the second embodiment described above is shown. exist Figure 7 Among them, 11 is a resistor, 12 is a capacitor, 13 is a buffer, and 14 is a node. like Figure 7 As shown, the resistor 11 is set on the input side of the input control signal, and the buffer 13 is set on the side of the gate voltage detection circuit 9 . A resistor 11 is connected to a buffer 13, and to a capacitor 12 between a node 14 disposed therebetween and a ground point. Because the resistor 11 and the capacitor 12 form a low-pass filter, once the input control signal shown in Figure 5 is input, the voltage 93 (dotted line) of the node 14 produces the passivation waveform shown in Figure 8 (that is, the change point changes slowly waveform). Here, the threshold voltage of buffer 13 is half of the input: V DD / 2, by inputting the voltage generated by the node 14 into the buffer, the rectangular wave 92 shown...
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