Electrostatic discharge protecting circuit

Abstract

The invention provides a static discharge protecting circuit, containing a semi- conductor substrate, first, second and third P-type traps all arranged on the substrate, where there is a first P+ doped region and a first N+ doped region arranged on the first P-type trap, the first P+ and N+ doped regions are grounded, there is a second P+ doped region and a second N+ doped region arranged on the second P+-type trap, the second P+ and N+ doped regions are connected to a power supply voltage VDD, and there is a third N+ doped region and a third P+ doped region as well as a fourth N+ doped region arranged on the third P-type trap, where the three doped regions outputs signals.

Description

technical field [0001] The present invention relates to an electrostatic discharge protection circuit, in particular to a circuit including PS (Positive to VSS), NS (Negative to VSS), PD (Positive to VDD), ND (Negative to VDD) and DS (VDD to VSS), etc. ESD protection circuit with five test modes. Background technique [0002] In recent years, the improvement of integrated circuit manufacturing process technology has enabled the size of integrated circuits (integrated circuits, ICs) such as complementary metal oxide semiconductor field effect (CMOS) transistors to be further reduced from submicron (submicron) To the deep sub-micron (deep-submicro), in order to reduce manufacturing costs and improve computing performance. However, the protection capability of integrated circuits against electrostatic discharge (ESD) will be weakened as the size shrinks. For example, when the channel width (channel width) of an output buffer (output buffer) element is set to 300 microns, the ...

AI Technical Summary

Problems solved by technology

[0018] 1. The electrostatic discharge protection circuit causes a load effect on its internal circuit and affects the overall performance;

[0019] 2. The leakage current of the electrostatic discharge protection circuit itself is too large, which increases power consumption;

[0020] 3. The driving voltage of the electrostatic discharge protection circuit is too high, and the electrostatic discharge current cannot be discharged in time to achieve the protective effect;

[0021] 4. The electrostatic discharge protection circuit itself can withstand insufficient electrostatic discharge voltage, which reduces the ability of the electrostatic discharge protection circuit to protect the internal circuit;

[0022] 5. The electrostatic discharge current cannot evenly flow through the electrostatic discharge protection circuit, so that even if the area of ​​the electrostatic discharge protection circuit is increased, there is no guarantee that the protection efficiency of the electrostatic discharge can be improved accordingly;

[0023] 6. In order to achieve comprehensive electrostatic discharge protection, the electrostatic discharge protection circuit needs at least three electrostatic discharge protection components, resulting in an increase in area;

[0024] 7. Electrostatic discharge protection circuits are sometimes completed using additional manufacturing processes, such as ESDimplant (injection), which increases cost expenditure; and

[0025] 8. The electrostatic discharge protection circuits currently on the market are not suitable for broadband radio frequency circuits

Images