Cross-thread register sharing technique

Abstract

A technique for sharing register resources within a microprocessor. Embodiments of the invention pertain to a register sharing technique within a microprocessor for rnultiple-threads of instructions that facilitates an optimal number of physical registers to be mapped to a desired numiber of logical registers without incurring significant hardware overhead.

Description

technical field [0001] The present invention relates to microprocessor architecture. More specifically, the present invention relates to techniques for sharing register resources within a microprocessor. Background technique [0002] In a typical high-performance superscalar microprocessor, one performance-enhancing technique is register renaming, in which logical registers referenced by instructions are mapped onto a larger set of physical registers. This physical register map helps eliminate false dependencies that can exist in logical register maps. Traditionally, a structure such as the register alias table (RAT) stores the "logical to physical" mapping, while another structure, such as the free list table ("freelist"), is left unused or "free " until they are allocated and used by the renaming unit. [0003] In a multi-threaded processor capable of executing several threads simultaneously, the technique for allocating physical registers from a free list may use a har...

AI Technical Summary

Problems solved by technology

[0008] figure 1 The prior art example of maximizes the free list size available to a particular thread, but requires the use of additional hardware, the ROB, to reallocate registers in the free list

on the other hand, figure 2 The prior art example of allows reallocating registers in the free list without using ROBs, but reduces the number of free list entries available to a single thread

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