Circuit module for realizing high-speed time division switching

Abstract

The invention is a circuit module for realizing high speed time division exchange, composed of an odd data memory, an even data memory, a control memory, a selector and a time sequence circuit. The synchronized 16-bit parallel data are written the odd and even data memories according to sequential addresses generated by the time sequence circuit, the control memory is written with data according to the address sent from the processor and red with data according to sequential address generated by the time sequence circuit. The output data of the control memory acts as read addresses of the data memories, thus achieving the purpose of time gas exchange. The two data memories both output a 16-bit data, and it obtains 16-bit parallel data exchanged by the selector. Thus, it solves the actual problem of single clock cycle realizing double-time gap exchange in high speed high-capacity SDH crossing. It can reduce circuit power consumption, and has high work reliability, beneficial to increasing the yield of IC chips.

Description

technical field [0001] The invention relates to the technical field of SDH broadband switching, in particular to a circuit module for realizing high-speed time-division switching in SDH cross-connect equipment. Background technique [0002] As a brand-new network transmission system, SDH network has rapidly become the backbone network of communication network due to its advantages in flexibility and convenience since it appeared in the 1990s. With the development of VLSI and SDH technology, the capacity of digital cross-connect equipment is increasing, and the speed is constantly improving, which also brings up new issues for the chip design of digital cross-connect. [0003] SDH digital cross-connect equipment (SDXC) is an important SDH network equipment. It completes the exchange of different high-speed signal branch signals, and can provide transparent connection and reconnection of ports between VCs composed of G.707. The core of SDH digital cross-connect equipment is ...

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Problems solved by technology

It is difficult to realize such high-speed multi-channel parallel data in FPGA or ASIC. Moreover, in high-speed SDH chips, the peripheral clock mostly uses 155M clock. Therefore, the data rate must be reduced, and the serial-to-parallel conversion The data width is 16 bits, and the data rate is 155M, but the goal to be achieved is that it must be exchanged by byte (time slot), and cannot be exchanged in units of 16 bits. It must be a clock cycle to exchange two time slots, so 16 bits How to exchange data according to time slots is a problem we face and solve

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