Circuit module for realizing high-speed time division switching

Abstract

A circuit module for realizing high-speed time-division switching is composed of two odd and even data memories, a control memory, a selector and a sequence circuit. The synchronized 16-bit parallel data is written into the odd and even data memories according to the sequential addresses generated by the sequential circuit, the data is written into the control memory according to the address sent by the processor, and the data is read from the control memory according to the sequential addresses generated by the sequential circuit. The data output by the control memory is used as the read address of the data memory, so as to achieve the purpose of time slot exchange. The two data memories output 16-bit data respectively, and the exchanged 16-bit parallel data is obtained through the selector. In order to solve the practical problem of realizing dual time slot switching in a single clock cycle in high-speed and large-capacity SDH cross-connection, the circuit structure can reduce circuit power consumption, work with high reliability, and help improve the production yield of integrated circuits.

Description

technical field [0001] The invention relates to the technical field of SDH broadband switching, in particular to a circuit module for realizing high-speed time-division switching in SDH cross-connect equipment. Background technique [0002] As a brand-new network transmission system, SDH network has rapidly become the backbone network of communication network due to its advantages in flexibility and convenience since it appeared in the 1990s. With the development of VLSI and SDH technology, the capacity of digital cross-connect equipment is increasing, and the speed is constantly improving, which also brings up new issues for the chip design of digital cross-connect. [0003] SDH digital cross-connect equipment (SDXC) is an important SDH network equipment. It completes the exchange of different high-speed signal branch signals, and can provide transparent connection and reconnection of ports between VCs composed of G.707. The core of SDH digital cross-connect equipment is ...

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Problems solved by technology

It is difficult to realize such high-speed multi-channel parallel data in FPGA or ASIC. Moreover, in high-speed SDH chips, the peripheral clock mostly uses 155M clock. Therefore, the data rate must be reduced, and the serial-to-parallel conversion The data width is 16 bits, and the data rate is 155M, but the goal to be achieved is that it must be exchanged by byte (time slot), and cannot be exchanged in units of 16 bits. It must be a clock cycle to exchange two time slots, so 16 bits How to exchange data according to time slots is a problem we face and solve

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