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Method for reducing power consumption in a state retaining circuit, state retaining circuit and electronic device

A technology for state retention and electronic devices, applied in the field of reducing power consumption of state retention circuits, state retention circuits and electronic devices

Inactive Publication Date: 2011-06-15
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But many systems must maintain their state during standby, and the state is lost by switching off the supply voltage, for example, in digital circuits where the state is determined by data stored in latches or state-holding circuits

Method used

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  • Method for reducing power consumption in a state retaining circuit, state retaining circuit and electronic device
  • Method for reducing power consumption in a state retaining circuit, state retaining circuit and electronic device
  • Method for reducing power consumption in a state retaining circuit, state retaining circuit and electronic device

Examples

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Embodiment Construction

[0044] figure 1 The state holding circuit diagram contains FETs with p-channel and n-channel. A FET with a p-channel is turned on when the voltage between the gate and source terminals is less than zero and turned off when the voltage between the gate and source terminals is greater than zero. A FET with an n-channel is turned on when the voltage between the gate terminal and the source terminal is greater than zero, and is turned off when the voltage between the gate terminal and the source terminal is less than zero.

[0045] This state holding circuit diagram shows a control unit 1 comprising an input 2 connected to the gate contact 4 of a transistor 36 and to the gate contact 12 of a transistor 38 . Transistor 36 is a FET with a p-channel and transistor 38 is a FET with an n-channel. The source terminal 6 and base terminal 7 of transistor 36 are connected to the standby power supply VDD_STANDBY. The drain terminal 8 of transistor 36 is connected to the drain terminal 1...

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PUM

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Abstract

A method for reducing the power consumption in a state retaining circuit during a standby mode is disclosed comprising, in an active state, providing a regular power supply and a standby power supply to the state retaining circuit; for a transition from an active state to a standby state, decreasing the regular power supply to ground level and maintaining the standby power supply thus providing the circuit elements of the state retaining circuit with enough power for retaining the state during standby mode; and for a transition from the standby state to the active state, increasing the regular power supply from its ground level to its active level, wherein the standby power supply is decreased to a lower level which is enough for retaining the state of the circuit elements in moving from an active state to a standby state; and the standby power supply is increased from its lower voltage to its active level in returning back into the active mode. The invention also discloses an electron device for reducing the power consumption in a state retaining circuit during the standby mode.

Description

technical field [0001] The present invention relates to a method, a circuit and an electronic device for reducing power consumption, in particular to a method, a state maintaining circuit and an electronic device for reducing the power consumption of a state maintaining circuit in standby mode. Background technique [0002] Leakage power is increasingly a drain on battery-operated devices, especially in state-holding circuits with long standby times. An obvious way to avoid leaks is to turn off power during standby. But many systems must maintain their state during standby, which is lost by switching off supply voltage, for example, in digital circuits where the state is determined by data stored in latches or state-holding circuits. [0003] US 5812463 provides a high speed high voltage latch with reduced leakage current and latchup vulnerability. This latch has a switching transistor between the programming supply and the output. When the latch input transitions to dri...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C5/14G11C11/41H03K3/356
CPCG11C5/14G11C5/143G11C5/148
Inventor M·加格K·B·R·劳J·D·J·皮内达德格伊维滋
Owner NXP BV
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