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Master apparatus and slave apparatus combined synchronous realization method

An implementation method and technology of the main device, applied in the direction of instruments, electrical digital data processing, etc., can solve the problems of low efficiency, do not support full-duplex transmission, do not support SPI interrupt transmission, etc., and achieve the effect of efficient transmission and improved transmission efficiency.

Inactive Publication Date: 2010-04-21
VIMICRO CORP
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Problems solved by technology

[0005] The disadvantage of this high-level protocol is that it does not support full-duplex transmission; it does not support SPI interrupt transmission, that is, the SSN must be kept low during the entire frame transmission; and, because the length of the command and address in the frame structure of the protocol is Fixed, so overhead and inefficiency when transferring small amounts of data

Method used

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  • Master apparatus and slave apparatus combined synchronous realization method
  • Master apparatus and slave apparatus combined synchronous realization method
  • Master apparatus and slave apparatus combined synchronous realization method

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Embodiment Construction

[0024] In the following description, well-known functions or structures will not be described in detail to avoid unnecessary confusion with the content of the present invention.

[0025] A method for realizing a high-level protocol frame structure for serial peripheral device interface bus data transmission, which is characterized in that: a variable-length data frame includes a frame header and a payload, and the change of the length is defined by the frame header.

[0026] Such as figure 2 shown. The data frame is composed of frame header and payload. The payload is the data to be transmitted, and its length can be changed. Because it carries variable data volume services, in order to improve transmission efficiency, a variable-length frame structure is adopted. In this high-level protocol, both the frame header and the payload are of variable length, and are defined by the frame header.

[0027] The header structure of the frame is as follows image 3 As shown, it cons...

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Abstract

The disclosed structure of frame as length variable data frame includes frame head and payload. Frame head defines variety of length. Using the said structure of frame makes protocol in high layer possible to support data transmission with addressing requirement between master device and slave devices. Using scheme of sub frame heads in the structure of frame makes protocol in high layer possibleto support communication in full duplex or half-duplex modes between master device and slave devices in high efficiency. In time of transferring low volume data, the method uses short head in structureof frame with variable length in order to raise transmission efficiency.

Description

technical field [0001] The invention relates to master-slave communication between electronic devices, in particular to a method for realizing joint synchronization of master equipment and slave equipment. Background technique [0002] Serial communication is a very important data communication method between the master device and the external device. Fewer data lines are required compared to a parallel communication bus. Serial Peripheral Interface (Serial Peripheral Interface, SPI) is a synchronous serial bus proposed by Motorola, which is used for data exchange between the master device and the peripheral device. The SPI bus is a master-slave communication mechanism, the master device is the master device, and the peripheral device is the slave device. It consists of 4 buses, namely the serial clock line (SCK), the master input / slave output data line (MISO), the master output / slave input data line (MOSI) and the slave active selection line (SSN) ). Compared with other...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/42
Inventor 王军金传恩谢律
Owner VIMICRO CORP
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