Invalidating translation lookaside buffer entries in a virtual machine (VM) system

Inactive Publication Date: 2005-04-14
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Because of this, system performance would suffer significantly if the TLB were invalidated on each such transition.
For this reason, a VM and its supporting VMM cannot easily share an address space.
If a VM

Method used

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  • Invalidating translation lookaside buffer entries in a virtual machine (VM) system
  • Invalidating translation lookaside buffer entries in a virtual machine (VM) system
  • Invalidating translation lookaside buffer entries in a virtual machine (VM) system

Examples

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Example

[0015] One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A translation lookaside buffer (TLB) in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of ope...

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Abstract

One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries.

Description

BACKGROUND [0001] 1. Field of the Invention [0002] This invention relates to virtual machines. In particular, the invention relates to translation lookaside buffers that support a virtual-machine system. [0003] 2. Description of Related Art [0004] A virtual-machine system is a computer system that includes a virtual machine monitor (VMM) supporting one or more virtual machines (VMs). A Virtual Machine Monitor (VMM) is a software program that controls physical computer hardware and presents programs executing within a Virtual Machine (VM) with the illusion that they are executing on real physical computer hardware. Each VM typically functions as a self-contained platform, controlled by a “guest” operating system (OS), i.e., an OS hosted by the VMM, which executes as if it were running on a real machine instead of within a VM. [0005] To accomplish this simulation, it is necessary for some operations within a VM (e.g., attempts to configure device hardware) to be trapped and emulated b...

Claims

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Application Information

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IPC IPC(8): G06F12/10
CPCG06F12/1036G06F2212/151G06F12/1027G06F9/30076
Inventor COTA-ROBLES, ERIK C.GLEW, ANDYJEYASINGH, STALINSELVARAJKAGI, ALAINKOZUCH, MICHAEL A.NEIGER, GILBERTUHLIG, RICHARD
Owner INTEL CORP
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