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Ball grid array package and process for manufacturing same

The integration of a collapsible spacer between the semiconductor die and heat spreader in the PBGA package addresses the issue of poor thermal dissipation in conventional PBGA packages by creating a direct thermal path and improving electrical performance, resulting in enhanced thermal and electrical performance.

Inactive Publication Date: 2006-10-05
UTAC HONG KONG LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This configuration improves thermal dissipation by providing a direct path for heat from the semiconductor die to the heat spreader, reduces electrical impedance by eliminating wire bonds, and allows for the manufacture of multiple packages with integrated heat spreaders in a single mold shot, enhancing both thermal and electrical performance.

Problems solved by technology

However, typical PBGA packages include a convoluted signal path, giving rise to high impedance and an inefficient thermal path which results in low thermal dissipation performance.
Because of the absence of a thermal path away from the semiconductor die 24, thermal dissipation in this package is poor.
This package suffers disadvantages, however, as heat must be dissipated form the semiconductor die 24, through the molding compound 28 and then through the heat spreader 32.

Method used

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Examples

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Embodiment Construction

[0024] Reference is not made to FIGS. 3A to 3J to describe a process for manufacturing a ball grid array integrated circuit package, referred to herein as a ball grid array package, according to an embodiment of the present invention. To simplify the description, the numerals used previously in describing FIG. 1 will be used again after raising the numerals by 100 where parts to be described correspond to parts already described.

[0025] Referring to FIG. 3J, the ball grid array package is indicated generally by the numeral 120. The ball grid array package 120 includes a substrate 122 having a plurality of conductive traces and a semiconductor die 124 flip-chip mounted to a first surface of the substrate 122 such that bumps 140 of the semiconductor die 124 are electrically connected to the ones of the plurality of conductive traces. A heat spreader 132 is disposed proximal to and spaced from the semiconductor die 124 by at least one collapsible spacer 136. A ball grid array 130 is di...

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PUM

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Abstract

A ball grid array integrated circuit package is manufactured by mounting a semiconductor die, to a first surface of a substrate such that bumps on the semiconductor die are electrically connected to conductive traces of the substrate. At least one collapsible spacer is mounted to at least one of a heat spreader, the semiconductor die and the substrate. The heat spreader is fixed to the at least one of the first surface of the substrate and the semiconductor die such that the at least one collapsible spacer is disposed therebetween. A ball grid array is formed on a second surface of the substrate, bumps of the ball grid array being electrically connected to the conductive traces and the integrated circuit package is singulated.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a Continuation of U.S. application Ser. No. 10 / 866,702, filed Jun. 15, 2004, which is a Division of U.S. application Ser. No. 10 / 647,696 (now U.S. Pat. No. 6,933,176), filed Aug. 25, 2003, which is a Continuation-In-Part of U.S. application Ser. No. 10 / 643,961 (now U.S. Pat. No. 6,987,032), filed Aug. 20, 2003, which is a Continuation-In-Part of U.S. application Ser. No. 10 / 323,657 (now U.S. Pat. No. 6,979,594), filed Dec. 20, 2002, which is a Continuation-In-Part of U.S. application Ser. No. 10 / 197,832 (now U.S. Pat. No. 6,800,948), filed Jul. 19, 2002. These applications, in their entirety, are incorporated herein by reference.FIELD OF THE INVENTION [0002] The present invention relates in general to integrated circuit packaging, and in particular to an improved ball grid array package with enhanced thermal characteristics and a unique method of manufacturing the ball grid array package. BACKGROUND OF THE INVENTION ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/00H01L23/055H01L23/24H01L23/433
CPCH01L21/561H01L21/563H01L2224/45144H01L2224/32245H01L2224/32225H01L2224/16225H01L2924/01033H01L24/48H01L2924/3011H01L2924/15331H01L2924/15311H01L2924/14H01L2924/01079H01L2924/01047H01L2924/01029H01L2924/01027H01L2924/01013H01L2924/01002H01L2224/97H01L2224/81815H01L2224/8121H01L2224/73253H01L23/055H01L23/16H01L23/24H01L23/3128H01L23/34H01L23/433H01L23/4334H01L23/49816H01L24/81H01L24/97H01L2224/16H01L2224/48091H01L2224/48227H01L2224/73204H01L2924/00014H01L2224/81H01L2924/00012H01L2924/00H01L2924/181
Owner UTAC HONG KONG LTD
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