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Substrate band gap engineered multi-gate pMOS devices

a technology of substrate band gap and multi-gate pmos, which is applied in the direction of semiconductor devices, basic electric elements, electrical equipment, etc., can solve the problems of degrading the performance of transistors, unable to control leakage current, and multi-gate devices are less efficient at controlling electric fields from source and drain regions

Inactive Publication Date: 2007-10-11
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0006] A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and

Problems solved by technology

However, as the dimensions of the transistors decrease the ability to control the leakage current becomes more difficult.
However, the use of such implants results in degraded performance of the transistor such as increasing the threshold voltage.
Despite the better control over the channel, the multi-gate devices are less efficient at controlling the electric fields from the source and drain regions.
The electric fields from the source and drain regions result in short-channel effects such as an increased leakage current at a given gate voltage in the subthreshold region of device operation.

Method used

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  • Substrate band gap engineered multi-gate pMOS devices

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Embodiment Construction

[0011] In the following description of substrate band gap engineered multi-gate pMOS devices numerous specific details are set forth in order to provide an understanding of the claims. One of ordinary skill in the art will appreciate that these specific details are not necessary in order to practice the disclosure. In other instances, well-known semiconductor fabrication processes and techniques have not been set forth in particular detail in order to prevent obscuring the present invention.

[0012] Embodiments of the present invention include band gap engineered multi-gate pMOS devices. In particular embodiments of the multi-gate pMOS device, the device is fabricated with a fin or body formed from a layer of material deposited over a substrate and a portion of the substrate. The layer of material deposited over a substrate and the substrate are selected such that the band gap of the material deposited over the substrate is narrower than that of the substrate. The difference in the b...

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Abstract

A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to the field of semiconductor devices and more specifically to controlling short-channel effects in multi-gate devices. [0003] 2. Discussion of Related Art [0004] During the past two decades, the physical dimensions of MOSFETs have been aggressively scaled for low-power, high-performance applications. The need for faster switching transistors requires shorter channel lengths. The continued decreasing size and need for low-power transistors makes overcoming the short channel effects of transistors necessary. However, as the dimensions of the transistors decrease the ability to control the leakage current becomes more difficult. To limit the amount of leakage current in a transistor current solutions involve strictly controlling the placement of the source and drain dopants within the active region of the transistor. Other techniques to combat the leakage current include implants in and a...

Claims

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Application Information

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IPC IPC(8): H01L27/10H01L29/739
CPCH01L29/66545H01L29/78687H01L29/78609H01L29/785
Inventor DOYLE, BRIAN S.JIN, BEEN-YIHKAVALIEROS, JACK T.DATTA, SUMAN
Owner INTEL CORP