High frequency differential voltage level shifter

Abstract

A design for a high speed differential voltage level shifter circuit arrangement utilizes both PFETs and NFETs controlled by inputs to determine the state of the outputs, which minimizes or eliminates contention on internal nodes when switching from one state to another. As a result, the design minimizes the adverse affects of mismatched NFET and PFET device strengths, and facilitates usage at high frequencies and for level shifting to a range of output voltage levels. The design is also adaptable for use in level shifting to higher or lower output voltages.

Description

FIELD OF THE INVENTION [0001]The invention is generally related to differential circuit arrangements, and in particular to differential voltage level shifters.BACKGROUND OF THE INVENTION [0002]Level shifting is commonly required in integrated circuit designs to shift the level of a signal between different voltage domains. Differential level shifters, for example, are commonly used to shift the common mode voltage of a differential input signal to either a higher or a lower voltage that is required for a particular circuit that will be processing the differential input signal.[0003]Particularly given the continued demand for faster circuit performance, differential level shifters, like other circuits, desirably must operate with as little rise and fall delay as possible. In many memory interfaces, for example, circuit delays must be minimized to the extent possible to maximize data transfer speeds. Differential level shifters are often used in memory interfaces, for example, to leve...

AI Technical Summary

Benefits of technology

[0006]The invention addresses these and other problems associated with the prior art by providing a design for a high speed differential voltage level shifter circuit arrangement that utilizes both PFETs and NFETs controlled by inputs to determine the state of the outputs, which minimizes or eliminates contention on internal nodes when switching from one state to another. As a result, the design minimizes the adverse affects of mismatched NFET and PFET device strengths, and facilitates usage at high frequencies and for level shifting to a range of output voltage levels. The design is also adaptable for use in level shifting to higher or lower output voltages.

Problems solved by technology

In conventional level shifters, contention often exists on internal nodes of the circuit during switching, as a new state often tries to overpower the current state of an internal node.

When there is a large difference between the voltage supply driving the input and the voltage supply driving the output, the contention takes longer to be resolved.

Also, because of this contention, conventional designs are susceptible to not switching correctly in the event of an NFET / PFET device strength mismatch.

A weak field effect transistor (FET) may not be able to overcome a stronger FET when attempting to switch, leaving internal nodes in an unknown state.

Images