N-Path Interleaving Analog-to-Digital Converter (ADC) with Offset gain and Timing Mismatch Calibration

Abstract

A system and method are provided for calibrating timing mismatch in an n-path time interleaved analog-to-digital converter (ADC). The method digitizes an analog signal with an n-path interleaved ADC, creating an interleaved ADC signal. In a first process, the phase of the interleaved ADC signal is rotated by 90 degrees, creating a rotated signal. This rotation may be accomplished using a finite impulse response (FIR) filter with taps at {0.5, 0, −0.5}, enabled as a derivative filter, or as a Hilbert transformation. In a parallel second process, the interleaved ADC signal is delayed, creating a delayed signal. The rotated signal is multiplied by the delayed signal to create a timing error signal. Using the timing error signal, timing errors are accumulated for the ADC signal paths, and corrections are applied that minimize timing errors in each of the n ADC signal paths.

Description

RELATED APPLICATIONS[0001]The following applications are incorporated herein by reference:[0002]CURRENT IMPULSE (CI) DIGITAL-TO-ANALOG CONVERTER (DAC), invented by Mikko Waltari, Ser. No. 141750,203, filed Jun. 25, 2015, filed Jun. 25, 2015, issued as U.S. Pat. No. 9,178,528[0003]TRAVELING PULSE WAVE QUANTIZER, invented by Mikko Waltari, Ser. No. 14 / 681,206, filed Apr. 8, 2015; issued as U.S. Pat. No. 9,098,072;[0004]N-PATH INTERLEAVING ANALOG-TO-DIGITAL CONVERTER (ADC) WITH BACKGROUND CALIBRATION, invented by Mikko Waltari, Ser. No. 14 / 531,371, filed Nov. 3, 2014, now U.S. Pat. No. 9.030,340;[0005]INTERLEAVING ANALOG-TO-DIGITAL CONVERTER (ADC) WITH BACKGROUND CALIBRATION, invented by Mikko Waltari et al., Ser. No. 14 / 511,206, filed Oct. 10, 2014, now U.S. Pat. No. 8,917,125;[0006]SYSTEM AND METHOD FOR FREQUENCY MULTIPLIER JITTER CORRECTION, invented by Mikko Waltari et al., Ser. No. 14 / 081,568, filed Nov. 15, 2013, now U.S. Pat. No. 8,878,577;[0007]TIME-INTERLEAVED ANALOG-TO-DIGITA...

AI Technical Summary

Benefits of technology

The patent describes a method for reducing timing errors in a system that uses multiple analog-to-digital converters (ADCs). The method involves creating a delayed signal by interleaving the ADC signal and then using it to multiply the rotated signal. This results in a timing error signal that can be used to accumulate timing errors in each of the ADC signal paths. By applying corrections to minimize these errors, the system can achieve better accuracy and reliability.

Problems solved by technology

As a result these timing and gain errors produce artifacts which in frequency domain show up as spectral images of the desired signal centered around every multiple of fs / n, where fs is the sampling rate of the composite ADC.

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