Inline monitoring of transistor-to-transistor critical dimension

Abstract

In one aspect of the present disclosure, a method is provided, the method including providing a test region in an upper surface region of a semiconductor substrate, forming a plurality of trenches in the test region, the trenches of the plurality of trenches having at least one of a varying width, a varying length, and a varying bridge between adjacent trenches, determining depth values of the trenches, and evaluating the risk of defects of gate electrodes to be formed on the basis of the depth values.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present disclosure relates to methods of inline monitoring of transistor-to-transistor critical dimensions (CDs) and test structures, and, more particularly, to a method for estimating the risk of defects of gate electrodes formed in at least one active region.[0003]2. Description of the Related Art[0004]As the semiconductor industry continues pushing the boundaries of Moore's Law, there is a constant drive to scale down the critical dimensions (CDs) of circuit elements of an integrated circuit (IC) in order to increase the functionality of ICs within the smallest footprints. A critical issue that has to be taken into account at advanced scaling is how close rows of arrays of transistors can be stacked upon one another (or with regard to the wafer in two dimensions). This is important because the source and drain of a transistor device are to be completely separated by the gate. In fully-depleted silicon-on-insulato...

AI Technical Summary

Benefits of technology

This patent describes a method and a test structure for a semiconductor device. The method involves forming test regions in an upper surface region of a semiconductor substrate, with a plurality of trenches having varying widths, lengths, and bridges between them. The depth values of the trenches are determined and used to evaluate the risk of defects in the adjacent active region. The test structure includes a test region and an active region, with at least one semiconductor device formed in the active region. The test region and the active region are separated by at least one insulating structure. The technical effect of this patent is to provide a tool for evaluating the quality of semiconductor devices during the manufacturing process.

Problems solved by technology

A critical issue that has to be taken into account at advanced scaling is how close rows of arrays of transistors can be stacked upon one another (or with regard to the wafer in two dimensions).

In fully-depleted silicon-on-insulator (FDSOI), for example, it is an issue that epitaxially grown raised source / drain regions may be overgrown around the ends of a gate structure, possibly leading to source / drain regions that are not completely separated.

However, as SORT takes place at an advanced stage during processing, there are high costs associated with manufacturing wafers which won't yield after the gate all the way down to SORT.

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