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Pcie traffic tracking hardware in a unified virtual memory system

a traffic tracking and hardware technology, applied in the field of computer science, can solve the problems of reducing the performance of the first processor during the measurement interval, the computing time needed to service the resulting page fault, and the performance reduction, so as to achieve the effect of quick and efficient identification

Active Publication Date: 2017-12-28
NVIDIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent describes a way to quickly and easily identify which parts of computer memory can be moved around without causing any problems. This makes it easier to change the way data is shared in the computer system.

Problems solved by technology

One drawback of this approach is that performance of first processor is reduced during the measurement interval.
This reduction in performance results from the computing time needed to service the resulting page faults.

Method used

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  • Pcie traffic tracking hardware in a unified virtual memory system
  • Pcie traffic tracking hardware in a unified virtual memory system
  • Pcie traffic tracking hardware in a unified virtual memory system

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Embodiment Construction

[0017]In the following description, numerous specific details are set forth to provide a more thorough understanding of the present invention. However, it will be apparent to one of skill in the art that the present invention may be practiced without one or more of these specific details.

[0018]Memory pages in a memory system that are shared between a first processor and a second processor may reside in the memory space of one of the two processors. One of the processors may be a central processing unit (CPU) while the other processor may be a parallel processing unit (PPU), such as a graphics processing unit (GPU). For example, a shared memory page may reside in the CPU memory system, even though both the CPU and the GPU access the memory page. Typically, CPU accesses of such a shared memory page have relatively low access times, while GPU accesses of a CPU-shared memory page may have relatively higher access times. If the GPU frequently accesses such a shared memory page, then GPU ...

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PUM

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Abstract

Techniques are disclosed for tracking memory page accesses in a unified virtual memory system. An access tracking unit detects a memory page access generated by a first processor for accessing a memory page in a memory system of a second processor. The access tracking unit determines whether a cache memory includes an entry for the memory page. If so, then the access tracking unit increments an associated access counter. Otherwise, the access tracking unit attempts to find an unused entry in the cache memory that is available for allocation. If so, then the access tracking unit associates the second entry with the memory page, and sets an access counter associated with the second entry to an initial value. Otherwise, the access tracking unit selects a valid entry in the cache memory; clears an associated valid bit; associates the entry with the memory page; and initializes an associated access counter.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit of United States provisional patent application entitled “PCIE TRAFFIC TRACKING HARDWARE IN A UNIFIED VIRTUAL MEMORY SYSTEM,” Ser. No. 61 / 785,641, filed Mar. 14, 2013, and of United States provisional patent application entitled “CPU-TO-GPU AND GPU-TO-GPU ATOMICS,” Ser. No. 61 / 800,004, filed Mar. 15, 2013, both of which are hereby incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]Embodiments of the present invention relate generally to computer science and, more specifically, to PCIe traffic tracking hardware in a unified virtual memory system.[0004]2. Description of the Related Art[0005]Multiprocessor systems typically include one or more shared memory spaces where two or more processers store and load data to and from a common set of memory pages. In such multiprocessor systems, a first processor may access shared memory pages over a communications path, ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F13/40G06F12/123G06F12/0806G06F12/0864G06F12/0875
CPCG06F13/404G06F12/123G06F2212/1016G06F12/0864G06F12/0875G06F12/0806G06F2212/1041
Inventor DULUK, JR., JEROME F.BUSCHARDT, CAMERONDEMING, JAMES LEROYFAHS, BRIANHAIRGROVE, MARKMASHEY, JOHN
Owner NVIDIA CORP
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