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Memory auto repairing circuit and associated method

Active Publication Date: 2018-06-14
ELITE SEMICON MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a memory auto repairing circuit and method that can automatically repair fail addresses in a memory. The circuit includes a decoding circuit, a latch enable circuit, and a first latch circuit. The decoding circuit compares a first input address with a plurality of fail addresses to generate a control signal. The latch enable circuit selectively generates a first enable signal based on the control signal. The first latch circuit receives the first input address and stores it when the first enable signal is received. If the first input address is identical to one of the plurality of fail addresses, the enable signal is prevented from being transmitted to the first latch circuit. This invention allows for efficient and automated repair of memory fail addresses, improving the reliability and performance of the memory.

Problems solved by technology

When a word line corresponding to a specific address is found defective, there is a good chance that two different redundancy word lines will be used for the specific address during the CP mode and the Final mode, causing a multi-selection problem.
In addition, certain problems need to be fixed during the FT mode.

Method used

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  • Memory auto repairing circuit and associated method
  • Memory auto repairing circuit and associated method
  • Memory auto repairing circuit and associated method

Examples

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first embodiment

[0012]FIG. 1 is a diagram illustrating a memory auto repairing circuit 100 according to the present invention. As shown in FIG. 1, the memory auto repairing circuit 100 comprises a decoding circuit 101, an inspecting circuit 102, a latch enable circuit 103, a latch circuit 104, and an E-fuse circuit 105. The decoding circuit 101 is arranged to receive an input address, e.g. an address A1 shown in FIG. 1, and decode the address A1 to determine if the address A1 corresponds to one of fail addresses FAm-FAn. If the address A1 corresponds to one of the fail addresses FAm-FAn, a redundancy word line previously allocated to the fail address will be accessed. It should be noted that the fail addresses FAm-FAn are usually stored in a plurality of E-fuse circuits. For clarity and simplicity, only the E-fuse circuit 104 relevant to this embodiment is depicted in FIG. 1. The decoding circuit 101 is further arranged to generate a control signal CS when the address A1 corresponds to one of the f...

second embodiment

[0014]FIG. 2 is a diagram illustrating a memory auto repairing circuit 200 according to the present invention. The memory auto repairing circuit 200 comprises a decoding circuit 201, an inspecting circuit 202, a latch enable circuit 203, latch circuits 204_1 and 204_2, E-fuse circuits 205_1 and 205_2, and a comparing circuit 206. In this embodiment, the address A1 has been stored into the latch circuit 204_1 according to the enable signal EN1 as in the embodiment of FIG. 1. The decoding circuit 201 is arranged to receive an input address, e.g. an address A2 shown in FIG. 2, and decode the address A2 to determine if the address A2 corresponds to one of the fail addresses FAm-FAn. If the address A2 corresponds to one of the fail addresses FAm-FAn, the redundancy word line previously allocated to the fail address is accessed. As mentioned in the embodiment of FIG. 1, the decoding circuit 201 is further arranged to generate the control signal CS when the address A2 corresponds to any of...

third embodiment

[0016]FIG. 3 is a diagram illustrating a memory auto repairing circuit 300 according to the present invention. The memory auto repairing circuit 300 comprises a decoding circuit 301, an inspecting circuit 302, a latch enable circuit 303, latch circuits 304_1 and 304_2, E-fuse circuits 305_1 and 305_2, and a comparing circuit 306, wherein the functions of the decoding circuit 301, the inspecting circuit 302, the latch enable circuit 303, the latch circuits 304_1 and 304_2, the E-fuse circuits 305_1 and 305_2, and the comparing circuit 306 are similar / identical to those described in the embodiment of FIG. 2. The only difference is the E-fuse circuit 305_1 is further arranged to generate a burned signal B1 to the latch circuits 304_1 when the address A1 is stored into the E-fuse circuit 305_1 as the fail address FA1. Once the burned signal B11 is received by the latch circuit 304_1, the latch circuit 304_1 will no longer store any input address. Likewise, the E-fuse circuit 305_2 is fu...

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Abstract

a memory auto repairing circuit including: a decoding circuit, a latch enable circuit and a first latch circuit, wherein the decoding circuit is arranged to compare a first input address with a plurality of fail addresses to generate a control signal; the latch enable circuit is arranged to selectively generate a first enable signal at least according to the control signal; and the first latch circuit is arranged to receive the first input address, and store the first input address when the first enable signal is received by the first latch circuit; wherein when the control signal indicates that the first input address is identical to one of the plurality of fail addresses, the enable signal is prevented from being transmitted from the latch enable circuit to the first latch circuit.

Description

BACKGROUND OF THE INVENTION1. Field of the Invention[0001]The present invention relates to a memory auto repairing circuit and an associated method.2. Description of the Prior Art[0002]Conventional memory requires two testing stages before leaving the factory; for example, a Chip Probing (CP) mode and a Final Test (FT) mode are executed to test memories. During a typical testing process, when a word line corresponding to an input address is found defective, a redundancy word line is accessed to repair the defective word line. When a word line corresponding to a specific address is found defective, there is a good chance that two different redundancy word lines will be used for the specific address during the CP mode and the Final mode, causing a multi-selection problem. In addition, certain problems need to be fixed during the FT mode. Therefore, a novel memory auto repairing circuit design is desired.SUMMARY OF THE INVENTION[0003]One of the objectives of the present invention is to...

Claims

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Application Information

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IPC IPC(8): G11C29/00G11C8/10G11C8/06G11C29/12G11C17/16
CPCG11C29/78G11C8/10G11C17/16G11C29/12G11C8/06G11C29/14G11C29/44G11C29/781G11C2029/1202G11C2029/1208G11C2029/4402G11C8/08G11C29/4401
Inventor YAO, TSE-HUACHEN, YI-FAN
Owner ELITE SEMICON MEMORY TECH INC
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