Method for defining alignment marks in a semiconductor wafer

Abstract

A lithography and etching method for forming an alignment mark (104) and at least one device feature (such as a shallow trench 105) on a wafer (99) is provided. The etching process (18) comprises: a first etching step (1811) for pre-defining at least one alignment mark (103) and a second etching step (1812) for defining desired semiconductor device patterns (such as a shallow trench 105) on said wafer surface and completing said at least one alignment mark (104).

Description

FIELD OF THE INVENTION[0001]The present invention generally relates to the manufacture of semiconductor devices on wafers, and more particularly to methods for forming alignment marks on semiconductor wafers, especially in conjunction with semiconductor devices employing shallow trench isolation (STI) or deep trench processes.BACKGROUND OF THE INVENTION[0002]In using certain types of semiconductor fabrication equipment, alignment marks around the periphery of the wafer are required to properly orient the wafer in a lithography tool. While such marks minimize the chance of alignment errors, there is a disadvantage in that the alignment marks are often required to be made before any other processing occurs (and thus the alignment marks are sometimes referred to as “zero” layer alignment marks). Since the definition of alignment marks has to be finished before any further step can follow, the creation of alignment marks adds a distinct step to the whole process which is time consuming ...

AI Technical Summary

Problems solved by technology

While such marks minimize the chance of alignment errors, there is a disadvantage in that the alignment marks are often required to be made before any other processing occurs (and thus the alignment marks are sometimes referred to as “zero” layer alignment marks).

Since the definition of alignment marks has to be finished before any further step can follow, the creation of alignment marks adds a distinct step to the whole process which is time consuming and costly, adding no value to the ultimate semiconductor devices being fabricated on the wafer.

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