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Memory system and computer system

a computer system and memory technology, applied in the field of logical physical conversion processing, can solve the problems of unintentional rewriting of programs, unintentional rewriting of binary data that the unselected cell stores, and shifting the threshold voltage of an unselected cell from 1 to 0

Inactive Publication Date: 2013-02-19
MEGACHIPS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0012]One object of the present invention is to provide a technique that does not allow data reading processing to be affected even if a “read disturb” phenomenon has occurred.

Problems solved by technology

However, since in the game machine and the like, a specific program is often read repeatedly, a possibility that the program is unintentionally rewritten is beginning to be pointed out.
As described in Japanese Patent Application Laid-Open No. 2008-192267, when binary data stored in a selected cell is repeatedly read, there is a possibility that a threshold voltage of an unselected cell shifts, and that binary data that the unselected cell stores is unintentionally rewritten from 1 to 0 (this is called a “read disturb” phenomenon).
Particularly, a bit error due to read disturb (read disturb error) is caused by repeatedly executing reading processing in a specific storage area of the flash memory without performing writing and erasing.
However, processing for repairing the above-described bit error is highly loaded processing involving reading of the data, error correction, erasing / writing of the data after the correction and the like.
Accordingly, if the repair processing is frequently performed, data reading processing from the NAND flash memory may be affected, so that an ongoing game may not normally behave.
Moreover, it is considered that the erasing / writing or the like causes the foregoing uncorrectable late defect (permanent late defect) in a block making up the NAND flash memory.

Method used

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  • Memory system and computer system
  • Memory system and computer system
  • Memory system and computer system

Examples

Experimental program
Comparison scheme
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first embodiment

[0132]In the present embodiment, a description is given of logical-physical conversion processing when after the above-described situation where no late defective block has occurred yet, a plurality of access requests to the memory 4 (e.g., reading requests) cause a tentative late defective block due to the read disturb phenomenon.

[0133]FIG. 9 is a diagram showing a configuration of the memory 4 according to the present embodiment.

[0134]As shown in FIG. 9, the reserve storage area 41 in the memory 4 has two management areas 41A, 41B. A configuration of the user information storage area 40 in FIG. 9 is the same as the configuration of the user information storage area 40 shown in FIG. 3. In the present embodiment, however, as will be described later, user information and duplicated use information are stored in the user information storage area 40. The first management area 41A in FIG. 9 is an area for individually storing / managing first physical address information of the initial de...

second embodiment

[0191]In the present embodiment, a description is given of repair processing (refresh processing) for the first block (user information block) 42 that is determined to be the tentative late defective block in the first embodiment. FIG. 17 is a flowchart showing operation of the computer system 1 according to the present embodiment.

[0192]Suppose while the power ON status in the memory card 3, which has been described in the first embodiment, is continuing, the memory card 3 receives, from the computer 2, a predetermined command that enables the memory card 3 to secure an idling period in the relationship with the computer 2 (step S201). When the memory card 3 receives the predetermined command, the memory controller 5 (e.g., the computing device 50) carries out the repair processing to the tentative late defective block (step S202).

[0193]Specifically, the memory controller 5 (e.g., the computing device 50) repairs the user information block 42 determined to be the tentative late defe...

third embodiment

[0201]In the first embodiment, the case where the number of (physical and logical) mirror areas is one has been described. That is, only one duplicate of the user information is prepared. In contrast, in a third embodiment, a case where there are a plurality of (physical and logical) mirror areas is described. That is, a plurality of duplicates of the user information are prepared. In the present embodiment, for simplification of the description, a case where the number of the (physical and logical) mirror areas is two is described.

[0202]FIG. 18A is a diagram schematically illustrating a logical space. Moreover, FIG. 18B is a diagram schematically illustrating a physical space before a late defective block occurs (that is, only the initial defect blocks have occurred).

[0203]In FIG. 18B, the user information storage area 40 of the memory 4 is made up of the 16 first blocks 42. In the respective first blocks 42, the first physical addresses PBA0 to PBA15 are set in the ascending order...

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PUM

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Abstract

A memory system according to the present invention includes, in addition to an computing device, a plurality of first blocks that are provided to store information including user information, and first physical addresses not overlapping one another are assigned to, respectively, and a plurality of second blocks that are provided to store first physical addresses of initial defect blocks out of the plurality of first blocks, respectively, wherein the computing device finds the first physical address corresponding a inputted given logical address, based on a given mirror logical address corresponding to the given logical address, and information stored in the second blocks.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to logical-physical conversion processing when a bit error occurs in a nonvolatile semiconductor memory due to read disturb and the like.[0003]2. Description of the Background Art[0004]Among nonvolatile memories, a NAND flash memory can bring about high integration and reduction in manufacturing cost by a simple circuit configuration, and make writing by a user easier, thereby being employed in an SD memory card and the like in abundance.[0005]Recently, the NAND flash memory has also been employed in a game machine and the like. When the NAND flash memory is used in the game machine and the like, writing does not occur, but continuous reading occurs. That is, the NAND flash memory is increasingly employed as a ROM.[0006]However, since in the game machine and the like, a specific program is often read repeatedly, a possibility that the program is unintentionally rewritten is beginning to be ...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G06F11/00
CPCG06F12/0246G06F2212/7201G06F2212/7202
Inventor TANAKA, SHINJI
Owner MEGACHIPS