Parallel processing using multi-core processor

Abstract

Disclosed are methods, systems, paradigms and structures for processing data packets in a communication network by a multi-core network processor. The network processor includes a plurality of multi-threaded core processors and special purpose processors for processing the data packets atomically, and in parallel. An ingress module of the network processor stores the incoming data packets in the memory and adds them to an input queue. The network processor processes a data packet by performing a set of network operations on the data packet in a single thread of a core processor. The special purpose processors perform a subset of the set of network operations on the data packet atomically. An egress module retrieves the processed data packets from a plurality of output queues based on a quality of service (QoS) associated with the output queues, and forwards the data packets towards their destination addresses.

Description

CLAIM OF PRIORITY[0001]This application claims the benefit of U.S. Provisional Application Ser. No. 61 / 740,374, filed on Dec. 20, 2012.FIELD OF INVENTION[0002]This invention generally relates to parallel processing. More specifically, the invention relates to parallel processing using multi-core processors.BACKGROUND[0003]A multi-core processor is a single computing component with two or more independent actual central processing units (called “cores”), which are the units that read and execute program instructions. Multi-core processors are used across many application domains including general-purpose, embedded, network, digital signal processing (DSP), and graphics. The improvement in performance gained by the use of a multi-core processor depends very much on the software algorithms used and their implementation. In particular, possible gains are limited by the fraction of the software that can be run in parallel simultaneously on multiple cores.[0004]In multi-core network proce...

AI Technical Summary

Benefits of technology

[0010]Since a single thread of the core processor performs all the set of network operations on the data packet, no state information or synchronization information is passed between processors, which results in faster and more efficient processing of data packets. Also, the number of memory reads and writes are minimized reducing the delay caused due to memory reads and writes. The discussed method, systems, structures and paradigms increase a number of effective operations per packet (EOPP), that is, the number of instructions that can be performed on the data packet to perform application related tasks.

Problems solved by technology

In particular, possible gains are limited by the fraction of the software that can be run in parallel simultaneously on multiple cores.

In multi-core network processing, a key challenge is how to exploit all the cores in these devices to achieve maximum networking performance, despite the performance limitations inherent in a symmetric multiprocessing operating system.

Significant resources are consumed in passing the state / synchronization information between the threads or the processors which reduces the availability of the resources for performing actual network application related tasks.

Therefore, the overhead of passing the state / synchronization information decreases the efficiency of the processor.

Further, in current architecture, the core processor does not perform any useful network related operation while waiting for the arrival of the next data packet.

In current systems that have multi-core processors with an array of pipelined special purpose cores, the multi-core processor is limited by the capabilities of the special cores and pipeline depth.

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