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Communication device possessing trouble detection function

A communication device and clock signal technology, which is applied in the directions of duplex signal operation, digital transmission system, data exchange network, etc., can solve the problems such as the lack of quantitative measurement of USB communication data, the increase in the cost of communication devices, and the difficulty in detection.

Inactive Publication Date: 2007-10-17
RENESAS TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, in a conventional communication device in which the transmitter and receiver operate on the same clock, the loopback operation is close to the actual USB communication in which there are frequency errors, transmission vibrations, phase fluctuations, and waveform fluctuations of the clock signal (duty ratio, etc.). It is not possible to conduct abnormal verification tests of communication devices under the operating conditions
In particular, for the clock data recovery circuit and elastic buffer circuit that absorb these frequency errors, transmit vibrations, waveform fluctuations, and phase fluctuations, and synchronize external data with the internal clock, anomaly detection is practically impossible in conventional loopback operations
[0007] Therefore, since the test must be performed using an expensive and high-speed test device that can apply USB data to which frequency errors, transmission vibrations, waveform fluctuations, and phase fluctuations are added, there is a problem that the manufacturing cost of the communication device becomes high.
[0008] In addition, conventional communication devices do not have a device for quantitatively measuring the vibration component of USB communication data, so it is difficult to detect whether the waveform quality (vibration component) of the transmitter is within the specification by loopback operation
Therefore, it is necessary to use expensive high-speed test equipment to verify the abnormality detection of whether the waveform quality of the transmitter is within the specification, which also leads to an increase in the test cost and the increase in the manufacturing cost of the communication device.
[0009] Moreover, in the traditional communication device, it is necessary to lead the multi-bit low-speed receiving data and sending data to the outside of the communication device during the loopback operation.
Therefore, it is necessary to provide a plurality of signal input and output paths, which also leads to an increase in the cost of the communication device from this point of view.
[0010] In addition, traditional communication devices are dedicated to half-duplex communication in which the output of the transmitter and the input of the receiver are directly connected. When abnormal detection involving multiple communication devices is involved, half-duplex communication must also be used for abnormal detection, which is different from using full-duplex communication. Compared with the case where the duplex detection is abnormal, the time for the abnormality detection test is longer, and from this point of view, there is also a problem that the manufacturing cost of the communication device increases.

Method used

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  • Communication device possessing trouble detection function
  • Communication device possessing trouble detection function
  • Communication device possessing trouble detection function

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0035] Referring to FIG. 1 , a communication device 10 according to Embodiment 1 of the present invention is a communication device that implements a physical layer (PHY layer) of USB2.0 Hi-speed (480MBPS).

[0036] Referring to FIG. 1 , a communication device 10 includes a receiver 100 , a transmitter 101 , a clock supply selection circuit 102 , a data comparison circuit 105 , signal switches 106 and 107 , and a vibration measurement circuit 108 .

[0037] The clock supply selection circuit 102 includes: a clock generation circuit 103 , a clock modulation circuit 104 and a clock switch 116 .

[0038] Clock generation circuit 103 multiplies external clock 142 from external oscillator 20 to generate internal clock signal CLKI and internal clock group 144 . The internal clock signal CLKI and the internal clock group 144 are high-speed clocks with a frequency of 480 MHz. For example, if the frequency of the external clock 142 is 12 MHz, the clock generation circuit 103 multiplie...

Embodiment 2

[0122] Referring to FIG. 11 , the communication device 10# of the second embodiment of the present invention is different from the communication device 10 of the first embodiment shown in FIG. 1 in the configuration of the clock supply selection circuit 102 . That is, in the communication device 10# of the second embodiment, the reference internal clock signal CLKI (480MHz) is directly supplied to the transmitter 101 as the transmission clock 146#, and the clock switch 116 is provided corresponding to the receiver 100 .

[0123] The clock switch 116 selects one of the internal clock signal CLKI used as the transmission clock 146# and the modulated clock signal 145 output by the clock modulation circuit 104, and supplies it to the receiver 100 as the reception clock 143#. The configuration of other parts of the communication device 10# is the same as that of the communication device 10 of the first embodiment, and detailed description thereof will not be repeated.

[0124] With...

Embodiment 3

[0128] In Embodiment 3, a test mode in which the half-duplex communication device 10 or 10# described in Embodiment 1 or 2 operates in a full-duplex mode and performs a high-speed fault detection test is described.

[0129] In the test mode of embodiment 3, in the communication device 10 and 10# shown in Fig. 1 and Fig. 11 respectively, signal switch 106 and 107 form signal between test communication node 147 and 148 and receiving node 134 and 135 path. That is, within each communication device 10, 10#, the signal path between its own communication nodes 132, 133 and receiving nodes 134, 135 is blocked.

[0130] FIG. 12 shows signal paths between communication devices in the test mode of the third embodiment.

[0131]Referring to FIG. 12 , in the test mode of the third embodiment, signals are transmitted and received between two communication devices 10A and 10B. Communication device 10A receives transmission data 201 as transmission data 130-A by transmitter 101, converts i...

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PUM

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Abstract

A clock supply select circuit controls supply of receive clock and transmit clock to a receiver and a transmitter. The clock supply select circuit includes a clock generate circuit generating internal clock of the reference, and clock modulate circuit generating a modulate clock signal modulated such that at least one of frequency fluctuation, phase fluctuation, waveform fluctuation and jitter is applied to the internal clock. In a normal operation mode, the internal clock is supplied as receive clock and transmit clock, and in a loopback operation mode, while the internal clock is supplied as receive clock, modulate clock signal is supplied as transmit clock.

Description

technical field [0001] The present invention relates to communication devices, and more particularly, to fault detection testing of communication devices. Background technique [0002] In various high-speed communication standards in recent years, the vibration component of the transmitted data has also increased along with the high transmission rate. In order to cope with such high-speed and high-vibration data, the operation of circuits for synchronizing external data with internal clocks, such as CDR (Clock Data Recovery: Clock Data Recovery) circuits and elastic buffers (Elasticity Buffer) in communication equipment The speed is also increased, and its configuration becomes complicated. [0003] For example, in USB2.0 (Universal Serial Bus Specification Revision 2.0), the latest serial interface communication standard that connects PCs (Personal Computer: Personal Computer) and peripheral devices, a high speed of 480MBPS (Mega-Bits PerSecond) is stipulated. serial comm...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L5/16H04L29/14H04L69/40
CPCH04L12/2697H04L43/50
Inventor 城田博史
Owner RENESAS TECH CORP