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IC packing substrate structure and its manufacture

A technology of integrated circuits and manufacturing methods, which is applied in the fields of printed circuit manufacturing, circuits, printed circuits, etc., and can solve problems such as the difficulty of plugging via holes, affecting the quality and quantity of production, and unrealistic plug holes, etc.

Inactive Publication Date: 2008-01-09
PHOENIX PRECISION TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] The above is the manufacturing process and structure of the substrate for integrated circuit packaging of the traditional technology. However, the substrate of the traditional technology-especially when making ultra-thin boards (0.1mm~0.04mm) and tiny through holes, because the via holes When plugging holes, it is extremely difficult, and it is easy to cause false plug holes and cavitation, which seriously affects the quality and quantity of production
[0012] From the above description, it can be known that the substrates for integrated circuit packaging manufactured by traditional technology, especially when manufacturing ultra-thin boards, have disadvantages such as difficult via hole plugging, difficult manufacturing process, and poor reliability.

Method used

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  • IC packing substrate structure and its manufacture
  • IC packing substrate structure and its manufacture
  • IC packing substrate structure and its manufacture

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0033] Please refer to FIG. 3A to FIG. 3H , the process steps of the first embodiment of the integrated circuit packaging substrate of the present invention include:

[0034] (a) Provide a copper foil base material 200, define several conductive columns 210 by etching, and roughen the surface of the conductive columns 210 by microetching to enhance their adhesion;

[0035] (b) Pressing a core insulating layer 220 and the copper foil base material 200, after pressing, one end of the conductor post 210 is buried in the core insulating layer 220, wherein the material of the core insulating layer 220 can be a Glass fiber prepreg (Prepreg) or thicker insulating resin;

[0036] (c) opening the core insulating layer 220 above each conductor post 210 with a laser, forming several blind holes 230, and removing the residual insulating material on the surface of the conductor post 210;

[0037] (d) Plating each of the blind holes with electroplating copper to form a solid blind hole 230...

no. 2 example

[0042] Please refer to FIG. 4A to FIG. 4H , the process steps of the second embodiment of the substrate for integrated circuit packaging of the present invention include:

[0043] (a) Provide a copper foil base material 300, define several conductive columns 310 by etching, and roughen the surface of the conductive columns 310 by microetching to enhance their adhesion;

[0044] (b) Pressing a core insulating layer 320 and the copper foil base material 300, after pressing, one end of the conductor post 310 is buried in the core insulating layer 320, wherein the material of the core insulating layer 320 can be a Glass fiber prepreg (Prepreg) or thicker insulating resin;

[0045] (c) opening the core insulating layer 320 above each conductor post 310 with a laser, forming several blind holes 330, and removing the residual insulating material on the surface of the conductor post 310;

[0046] (d) Plating a layer of copper 340, 330a on the core insulating layer 320 and several bli...

no. 3 example

[0052] Please refer to FIG. 5A to FIG. 5G , the process steps of the third embodiment of the substrate for integrated circuit packaging of the present invention include:

[0053] (a) Provide a copper foil base material 400, define several conductive columns 410 by etching, and roughen the surface of the conductive columns 410 by microetching to enhance their adhesion;

[0054] (b) Pressing a core insulating layer 420 and the copper foil base material 400, after pressing, one end of the conductor post 410 is buried in the core insulating layer 420, wherein the material of the core insulating layer 420 can be a Glass fiber prepreg (Prepreg) or thicker insulating resin;

[0055] (c) opening the core insulating layer 420 above each conductor post 410 with a laser, forming several blind holes 430, and removing the residual insulating material on the surface of the conductor post 410;

[0056] (d) Plating a layer of copper 440, 430a on the core insulating layer 420 and several blin...

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Abstract

A fabricating method of encapsulating base plate for integrated circuit includes the steps as to define out several conductor columns on a copper foil base material, to cover one or several layers ofcore insulation on the copper foil base material with one end of conductor column being buried in the core insulation layer, to open core insulation layer at above point of each conductor column to form several blind holes and then to carry out a full plating or plating one layer of copper on each blind hole, to plate one copper face layer on the upper side surface of core insulation layer, to etch for defining out upper and down circuit layer and to cover a protection layer with welding proof material on each of it for the final product.

Description

field of invention [0001] The invention relates to a substrate structure for integrated circuit packaging and a manufacturing method thereof, in particular to a substrate structure and a manufacturing method which are applied to making ultra-thin substrates and can omit the step of plugging holes. Background of the invention [0002] After the chip (IC) passes through hundreds of process steps, a complex integrated circuit with specific functions will be formed in the chip. The chip must be packaged on the substrate before the chip can be combined with the circuit on the circuit board. [0003] Please refer to FIG. 1 , which is a schematic structural diagram of a conventional integrated circuit packaging substrate, which mainly includes a substrate 10 , an upper circuit layer 60 a , a lower circuit layer 60 b and several via holes 50 . [0004] The substrate 10 is an insulating material, the upper circuit layer 60a is arranged on the upper surface of the substrate 10, and th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/48H01L21/60H01L23/12H05K3/00
CPCH01L2924/15311H01L2224/48091H01L2224/48227H01L2924/00014
Inventor 许诗滨
Owner PHOENIX PRECISION TECH CORP