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Multi-exponent storage unit

A multi-level storage and gate technology, applied in information storage, static memory, read-only memory, etc., to achieve the effect of increasing storage capacity

Inactive Publication Date: 2008-02-27
POWERCHIP SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] However, the existing SONOS read-only memory can usually store one bit of data in a single storage unit, but because the application software of the computer is getting larger and larger, the required memory capacity is also increasing, so the existing SONOS storage unit The structure and manufacturing method must be changed to meet the trend

Method used

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Embodiment Construction

[0034] 2A to 2F are schematic diagrams illustrating a manufacturing process of a multi-level memory cell according to a preferred embodiment of the present invention. Referring to FIG. 2A , the manufacturing method of the multi-level memory cell firstly provides a substrate 200 , and the substrate 200 is, for example, a P-type semiconductor substrate. A tunneling dielectric layer 202 is then formed on the substrate 200, and a tunneling dielectric layer with a thickness of, for example, 20-40 angstroms is formed on the substrate 200 by a chemical vapor deposition process (Chemical Vapor Deposition, CVD). 202. The material thereof is, for example, silicon oxide, so the tunnel dielectric layer 202 can also be called the bottom oxide layer 202 . Next, a layer of charge trapping layer 204 is formed on the tunnel dielectric layer 202, and a charge trapping layer 204 is formed on the tunnel dielectric layer 202 with a thickness of, for example, 40 angstroms to 60 angstroms by using ...

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Abstract

Multistage memory cell comprises substrate, dielectric layer through channel, charge trap layer, top dielectric layer, grid pole, and source pole / drain pole. The dielectric layer through channel, charge trap layer and top dielectric layer are configured in sequence between substrate and grid pole. Source pole / drain pole in substrate are positioned at two sides of grid pole. At least two blocks are divided in the top dielectric layer. Each block is in different thickness. Thus, when voltage is applied to memory cell, each block possesses different electric field intensity between grid pole and substrate so as to cause different electric charge stored in charge trap layer. The invention makes single memory cell possible to store multiple bits and increase memory capacity of cell.

Description

technical field [0001] The present invention relates to a semiconductor device, and more particularly to a multi-level memory cell. Background technique [0002] Electrically Erasable and Programmable Read-Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM) has the ability to store, read, and erase data multiple times, and the stored data will not change after power off. The advantage of disappearing, so it has become a non-volatile memory component widely used in personal computers and electronic equipment. [0003] The electrically erasable and programmable read-only memory uses doped polysilicon to make floating gates (Floating Gate) and control gates (Control Gate). When the memory is programmed, the electrons injected into the floating gate are uniformly distributed throughout the polysilicon floating gate layer. However, when the tunnel oxide layer under the polysilicon floating gate layer has defects, it is easy to cause leakage current of the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/105H01L27/115G11C16/00
Inventor 张格荥黄丘宗
Owner POWERCHIP SEMICON CORP