Method for restricting poly-silicon pattern

Abstract

The provided method to limit polysilicon pattern comprises: forming a polysilicon on a substrate, and a pattern screen layer on top; taking the first etching for the exposed polysilicon layer to form multiple concave holes, stripping the screen layer with gas without O2; finally, etching secondly to let the holes up to substrate surface.

Description

technical field [0001] The present invention relates to a method for defining a polysilicon pattern, in particular to a method for etching a polysilicon layer. Background technique [0002] With the advancement of semiconductor process technology, it is a current trend to integrate N-type polysilicon and P-type polysilicon processes to obtain gate structures with different electrical properties, thereby satisfying different requirements of semiconductor devices. Since the dopants required for N-type polysilicon and P-type polysilicon are different, the two also have different results in terms of process performance. For example, as the line width of semiconductor devices continues to shrink, the N-type / P The profile of the type polysilicon layer, the after-etch-inspection critical dimension (AEI CD) line width, and the uniformity of the gate oxide layer remaining after etching have all developed to bottlenecks. Therefore, how to provide an ideal method to define the pattern...

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Problems solved by technology

When carrying out the etching process, since the etching rate of the doped polysilicon layer 14a is much higher than that of the undoped polysilicon layer 14b, the two sides of the doped polysilicon layer 14a are caused to have side erosion 18, so the N-type / P-type cannot be made The profile of the polysilicon layer is close to the critical line width after etching

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