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Two layer LTO backside seal for a wafer

A wafer and backside technology, applied in the process field of low temperature oxide deposition

Inactive Publication Date: 2008-08-06
SILTRONIC AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This results in non-uniformity in epitaxial dopant distribution that is outside the tolerance of most device manufacturers

Method used

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  • Two layer LTO backside seal for a wafer
  • Two layer LTO backside seal for a wafer
  • Two layer LTO backside seal for a wafer

Examples

Experimental program
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Embodiment Construction

[0013] figure 1 Denotes a silicon wafer with two LTO layers forming a backside seal. The substrate 1 is doped (p-type or n-type) silicon. Layer 2 is made using high silane (SiH 4 ) flow using high frequency RF at high power to form a low stress LTO layer. Layer 3 is deposited on layer 2 using high and low frequency RF at high power, thereby providing a high density high stress LTO layer which has a lower etch rate during the subsequent cleaning process.

[0014] The low stress LTO layer 2 controls the geometry of the wafer to minimize warpage of the wafer. This low stress LTO layer also serves to improve edge blurring during epitaxy.

[0015] The high stress LTO layer has a high density and thus a low etch rate. This allows the backside seal to maintain the low stress LTO layer during the subsequent cleaning process since only a small amount of the highly stressed LTO layer is available for etching. The low stress LTO layer also has a high deposition rate, which means a ...

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Abstract

A two layer LTO backside seal for a wafer. The two layer LTO backside seal includes a low stress LTO layer having a first major side and a second major side, the first major5 side of the low stress LTO layer adjacent to one major side of the wafer. The two layer LTO backside seal further includes a high stress LTO layer having a first major side and second major side, the first major side of the high stress LTO layer adjacent the second major side of the low stress LTO layer.

Description

technical field [0001] The present invention relates to a process for low temperature oxide (LTO) deposition using low pressure plasma enhanced chemical vapor deposition (LPPECVD) for wafer backside sealing, and in particular to two layer LTO backside sealing. Background technique [0002] Autodoping is a problem that occurs in silicon wafers used for epitaxial deposition. During the thermal cycling of the epitaxy process, the highly doped (p + ) silicon substrate diffuses dopant atoms through the backside of the substrate, resulting in an unintentional overdoping effect on the front side of the wafer. This is most noticeable at the edge of the wafer. This results in non-uniformity in epitaxial dopant distribution that is outside the tolerance of most device manufacturers. [0003] The backside layer on the wafer reduces autodoping effects. [0004] SiO is deposited using various techniques 2 Floor. These technologies can be roughly divided into atmospheric and low pre...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/22
CPCH01L21/2205H01L21/02164H01L21/02211
Inventor 李金星欧文勤
Owner SILTRONIC AG
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