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Decode circuit and method of wittbi decoder

A decoding method and decoding circuit technology are applied in the decoding circuit and field of Viterbi decoder, and can solve complex problems and the like

Inactive Publication Date: 2009-04-08
MEDIATEK INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0019] Therefore the present invention provides a kind of Viterbi decoding circuit and method, can solve the complex trellis diagram of Viterbi trellis diagram after longitudinal arrangement, and do not need a large number of registers to process data and can also achieve the purpose of high-speed Viterbi decoding

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  • Decode circuit and method of wittbi decoder
  • Decode circuit and method of wittbi decoder
  • Decode circuit and method of wittbi decoder

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Embodiment Construction

[0064] Figure 8 Shown is a flow chart of the method of the Viterbi decoder of the present invention. exist Figure 8 In, first establish the trellis diagram (S70) that cooperates with Viterbi decoder (such as image 3 shown). In order to solve the bottleneck of the ACS, the trellis diagram of the Viterbi decoder is reorganized, and the methods of reorganization include two methods: horizontal sorting and vertical sorting. by Figure 9A As shown in the original trellis diagram and n=2 as an example, in Figure 9B As shown, the original grid diagram is sorted horizontally. The so-called horizontal sorting is to merge the grids of the original n states into one state. Although the bottleneck of ACS also exists, the bottleneck time is lengthened from 1T to nT. The speed limit of the Viterbi decoder is thus relieved.

[0065] Figure 9C As shown, the original trellis is sorted vertically. exist Figure 9C In the process, the trellis diagram matching the Viterbi decoder is...

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Abstract

The circuit comprises a branch measuring unit, an adding-comparing-selecting unit and a path memory unit which consists of a retroaction write in register array, a wait register array and a decoding register array. The run length limited code is used to solve complex cellular drawing after Witt ratio decoder cellular drawing is longitudinal-ordered and the register array can undertake some other actions at different time so it is unnecessary to use many registers to process data, but decoding aim by using high-speed Witt ratio decoder can also be achieved.

Description

technical field [0001] The present invention relates to a decoding circuit and method of a Viterbi (Viterbi) decoder in the PRML (Partial Response Maximum Likelihood) system of the optical disc, specifically, relates to the PRML system in the optical disc Such a Viterbi decoder decoding circuit and method, the circuit and method use RLL code (Run Length Limited Code, run length limit code) to effectively solve the complex trellis diagram of the Viterbi decoder after vertical arrangement , and does not require a large number of registers to process data. Background technique [0002] In a PRML system of an optical disc such as a DVD (digital versatile disc, digital versatile disc), a trellis diagram (trellisdiagram) can be used to describe the characteristics of a transmission channel (transmission channel) with memory. For example, the input signal EFMP of a DVD channel is a binary signal, and the channel memory length is 2, so there are 4 states on the trellis diagram, and...

Claims

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Application Information

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IPC IPC(8): H03M13/00
Inventor 郭弘政吴文义
Owner MEDIATEK INC