Method and system for multiple GPU support

Abstract

Supporting multiple graphics processing units (GPUs) comprises a first path coupled to a north bridge device and a first GPU, which may include a portion of the first GPU's total communication lanes. A second communication path may be coupled to the north bridge device and a second GPU and may include a portion of the second GPU's total communication lanes. A third communication path may be coupled between the first and second GPUs directly or through one or more switches that can be configured for single or multiple GPU operations. The third communication path may include some or all of the remaining communication lanes for the first and second GPUs. As a nonlimiting example, the first and second GPUs may each utilize an 8-lane PCI express communication path with the north bridge device and an 8-lane PCI express communication path with each other.

Description

technical field [0001] The present invention relates to graphics processing, and more particularly to a method and system for supporting multiple graphics processing units by converting one connection to multiple connections. Background technique [0002] The demand for graphics display in computer applications has been increasing, which drives the development of higher-level graphics processing capabilities. Computer applications such as computer games usually require a large amount of calculations to present complex and high-definition graphics. Therefore, it is possible to meet consumer needs by improving graphics computing capabilities and changing the internal structure of computers. [0003] Especially for personal computers, in order to meet entertainment and multimedia applications, such as high-resolution video and the latest 3D games, its design orientation has focused on increasing system bandwidth. The proposed approach to meet this design requirement frees up t...

AI Technical Summary

Problems solved by technology

In this prior art, the aforesaid multiple graphics processing units 30, 36 are still supported, and the northbridge chip 14 is connected to the graphics processing units 30, 36 by having eight PCIe channels 33 and another having eight PCIe channels 38, To make it support point-to-point communication between the north bridge chip 14 and the graphics processing units 30, 36, additional logic gates are configured in the north bridge chip 14 to realize this architecture, but thus reducing the performance of the north bridge chip 14.

On the other hand, the interconnection of graphics processing units 30, 36 also encounters the time delay in the prior art as shown in Figure 2, so the existing computer system 40 is still not ideal and satisfactory

[0017] Therefore, so far there is no technology available to overcome the deficiencies and shortcomings of the above-mentioned prior art

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