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Decoding device and decoding method

A decoding device and LDPC code technology, applied in the direction of error detection coding, error correction/detection using linear codes, error correction/detection using block codes, etc., can solve the difficulty of memory access control, and it is difficult to avoid simultaneous reading and writing Entry and other issues

Inactive Publication Date: 2009-07-29
SONY CORP
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Problems solved by technology

In this case, generally, there is such a problem that it is not easy to avoid simultaneous reading from different addresses of the memory, or simultaneous writing to different addresses of the memory, and memory access control is difficult
[0117] Memory access control is difficult in a method of performing calculations of messages in parallel in units of several calculations

Method used

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  • Decoding device and decoding method
  • Decoding device and decoding method
  • Decoding device and decoding method

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Embodiment Construction

[0198] Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the accompanying drawings.

[0199] Figure 15 An example of a 30×9 parity check matrix divided into 5×5 matrix units is shown. Figure 15 check matrix and Figure 8 The parity check matrix shown in is the same.

[0200] exist Figure 15 In , the check matrix is ​​represented by a combination of the following matrices: 5×5 identity matrix; the elements of the identity matrix are replaced by 0—a matrix of one or more 1s (hereinafter referred to as "quasi-identity matrix" in appropriate places) ); an identity matrix or a matrix in which a quasi-identity matrix is ​​cyclically shifted (hereinafter, referred to as a “shift matrix” where appropriate); two or more (multiple ) (hereinafter referred to as “sum matrix” where appropriate); and a 5×5 0 matrix. Depend on Figure 15 The LDPC code represented by the check matrix of has a coding rate of 2 / 3 a...

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Abstract

Provided are a decoding device and a decoding method for realizing LDPC code decoding capable of limiting circuit size, limiting operating frequency to a sufficiently feasible range, and easily controlling memory access. The parity check matrix of the LDPC code consists of a combination of a p×p identity matrix, one or more identity matrices in which 1s are changed to 0s, their cyclic shifts, their sum, and p×p 0 matrices. While the variable node calculation component (319) simultaneously performs P variable node calculations, the check node calculation component (313) simultaneously performs P check node calculations.

Description

technical field [0001] The present invention relates to a decoding device, a decoding method and a program. More specifically, the present invention relates to a decoding device and a decoding method for decoding a code encoded using a low-density parity-check code (LDPC code), and a program thereof. Background technique [0002] In recent years, for example, research has progressed remarkably in communication fields such as mobile communications and deep space communications, and broadcasting fields such as terrestrial wave or satellite digital broadcasting. Along with this situation, research on coding theory for making error correction coding and decoding efficient has been actively conducted. [0003] As a theoretical limit of code performance, the Shannon limit expressed by the so-called Shannon (C.E. Shannon) channel coding theorem is well known. With the aim of developing codes showing performance close to this Shannon limit, research into coding theory has been car...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/09H03M13/19
Inventor 横川峰志官内俊之饭田康博
Owner SONY CORP
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