Method for manufacturing metal-oxide semiconductor transistor

Abstract

A method for manufacturing metal oxide semiconductor transistors. The method includes first forming a first gate structure and a second gate structure on a substrate, wherein the size of the first gate structure is larger than that of the second gate structure. Then, a first lightly doped region is formed in the substrate on both sides of the first gate structure, and then a lightly doped annealing step is performed. Afterwards, a second lightly doped region is formed in the substrate on both sides of the second gate structure. Then, a first spacer is formed on the sidewall of the first gate structure, and a second spacer is formed on the sidewall of the second gate structure at the same time. Subsequently, a first source / drain region is formed in the substrate on both sides of the first spacer, and a second source / drain region is formed in the substrate on both sides of the second spacer. Then, a source / drain annealing step is performed.

Description

technical field [0001] The invention relates to a manufacturing method of an integrated circuit element, in particular to a manufacturing method of a complementary metal oxide semiconductor transistor and a metal oxide semiconductor transistor. Background technique [0002] Metal-oxide-semiconductor transistors are the basic units in modern logic circuits. Each transistor consists of a gate, a source / drain region (S / D region) in the substrate on both sides of the gate, and a source The channel (channel) between the region and the drain region constitutes. When the process of metal oxide semiconductor transistors progresses to the micron level, the channel between the source / drain regions will become shorter, so short channel effects and hot carrier effects will occur. (hot carrier effect) and other problems, and then cause the component to fail to operate. Therefore, the lightly doped region (LDD) structure is used in the source / drain design of transistors with micron-leve...

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Problems solved by technology

As mentioned above, the diffusion area of ​​an improper LDD structure will affect the electrical behavior of the entire component, and even cause component failure

Especially, for small-sized components, too high lateral diffusion will lead to the generation of short channel effect, or the problem of electrical breakdown (punch through)

For large-scale devices, too low lateral diffusion will form a high impedance at the overlap between the LDD and the gate and reduce the saturation drain current, thereby affecting device performance

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